Halbleiteranordnung

Details

Veröffentlichungs-Nr.

EP4794506

Anmeldetag

15. Oktober 2025

Veröffentlichung

19. August 2026

Rechtsraum

EP

IPC

H10P58/00, H10P54/92

Abstract

A semiconductor device includes a substrate including a chip region and a scribe lane region including a chip adjacent region, a chip adjacent crossing region, and a peripheral crossing region; a passivation layer; row trenches disposed between the boundary between the chip adjacent crossing region and a first boundary of the peripheral crossing region and the boundary between the chip adjacent crossing region and the chip adjacent region, in a direction crossing the first boundary, and disposed in the passivation layer; and column trenches disposed between the boundary between the chip adjacent crossing region and a second boundary of the peripheral crossing region and the boundary between the chip adjacent crossing region and the chip adjacent region, in a direction crossing the second boundary, and disposed in the passivation layer.

Anmelder

Firma

SK hynix Inc.

Land

🇰🇷 Südkorea

Fachgebiete