Musterungsverfahren zur Verwendung in der Halbleiterverarbeitung
Anmelder: Imec VZW 🇧🇪
Details
- Veröffentlichungs-Nr.
- EP4796998
- Anmeldetag
- 20. Februar 2025
- Veröffentlichung
- 26. August 2026
- Rechtsraum
- EP
Abstract
A pattern is produced in a die area (25) of a layer (30,33) formed on a support substrate (32) by at least two process sequences, each comprising a lithography step and an etch step, performed in adjacent subportions of the die area. One or more parallel line shaped features (28) of the pattern extend from the first subportion (25a) of the die area to the second subportion (25b), i.e. across the border (27) between the die areas. Mutually aligned and spaced apart first and second parts of the line features are printed in the respective process sequence steps and transferred to the layer in the form of negative or positive pattern features in the patterned layer, i.e. in the form of trenches (28'a,28'b) in the layer or in the form of lines separated by mutually aligned trenches (37a;37b). In either case, directional etching is thereafter applied to stretch the aligned trenches and thereby obtain the desired line features (28) extending from one subportion of the die area to the other subportion.
Anmelder
- Firma
- Imec VZW
- Land
- 🇧🇪 Belgien
Imec ist ein belgisches Forschungszentrum mit Sitz in Leuven, das auf Nanoelektronik, Halbleitertechnologie und digitale Technologien spezialisiert ist.
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