Vorrichtung und Verfahren zur Matrixmultiplikation zwischen Produkten

Details

Veröffentlichungs-Nr.

EP4797083

Anmeldetag

20. Februar 2026

Veröffentlichung

26. August 2026

Rechtsraum

EP

IPC

G06F9/30

Abstract

An example processor includes vector registers to store sub-matrices of two source matrices and execution circuitry to perform a cross-product matrix multiplication. A decoder interprets an instruction specifying the source matrices and the operation. The execution circuitry multiplies each combination of sub-matrices from the two source matrices-first with first, first with second, second with first, and second with second-to generate four corresponding sub-matrices of a result matrix, which are stored in a third vector register. This architecture enables efficient parallel matrix computations for high-performance processing tasks.

Anmelder

Firma

Intel Corporation

Land

🇺🇸 USA

Fachgebiete