Vorrichtung und Verfahren zur Blockweisen Matrixmultiplikation mit mehreren Registern

Details

Veröffentlichungs-Nr.

EP4797084

Anmeldetag

23. Februar 2026

Veröffentlichung

26. August 2026

Rechtsraum

EP

IPC

G06F9/30

Abstract

An example processor executes an instruction having an operand field to indicate a multi-register cross-product matrix multiplication to be performed with the first plurality of sub-matrices and the second plurality of sub-matrices to generate the third plurality of sub-matrices. Execution circuitry execute the instruction, the execution circuitry to generate each sub-matrix of the third plurality of sub-matrices in a corresponding vector register of the third plurality of vector registers by multiplying a sub-matrix in a corresponding vector register of the first plurality of vector registers and a sub-matrix in a corresponding vector register of the second plurality of vector registers.

Anmelder

Firma

Intel Corporation

Land

🇺🇸 USA

Fachgebiete