Analoge Speicherinterne Rechnervorrichtung für Neuronales Netzwerk

Details

Veröffentlichungs-Nr.

EP4797264

Anmeldetag

16. Januar 2026

Veröffentlichung

26. August 2026

Rechtsraum

EP

Abstract

An analog in-memory computing device (100) for a neural network is provided. The analog in-memory computing device (100) includes a memristor array (120) and a readout circuit (140). The readout circuit (140) includes a differential amplifier circuit (AMP3, AMP4, AMP5, AMP6) and a plurality of current-voltage conversion circuits (CVC31 to CVC3n, CVC41 to CVC4n, CVC51 to CVC5n, CVC61 to CVC6n). A first input terminal of the differential amplifier circuit (AMP3, AMP4, AMP5, AMP6) is coupled to a reference voltage source (Vref). Each second input terminal of the differential amplifier circuit (AMP3, AMP4, AMP5, AMP6) is coupled to a corresponding column line of the memristor array (120). A first terminal of each current-voltage conversion circuit (CVC31 to CVC3n, CVC41 to CVC4n, CVC51 to CVC5n, CVC61 to CVC6n) is coupled to a corresponding column line. A second terminal of each current-voltage conversion circuit (CVC31 to CVC3n, CVC41 to CVC4n, CVC51 to CVC5n, CVC61 to CVC6n) is coupled to a corresponding output terminal of the differential amplifier circuit (AMP3, AMP4, AMP5, AMP6). Each current-voltage conversion circuit (CVC31 to CVC3n, CVC41 to CVC4n, CVC51 to CVC5n, CVC61 to CVC6n) outputs a readout result voltage corresponding to a corresponding column line.

Anmelder

Firma

OmniVision Technologies, Inc.

Land

🇺🇸 USA