Datenverarbeitungssystem mit Geteilter Transaktionsverbindung in Kommunikation mit einer Peripheren Fifo-Struktur

Details

Veröffentlichungs-Nr.

EP4804042

Anmeldetag

26. Februar 2026

Veröffentlichung

9. September 2026

Rechtsraum

EP

Abstract

A data processing system (100) includes a requestor (104), a split transaction interconnect (102), and address mapping circuitry (110). The requestor (104) issues block access requests (1) to a target peripheral (112). The target peripheral (112) includes a set of first-in first-out structures (FIFOs) (130) which buffer incoming or outgoing data. The split transaction interconnect (102) has a requestor port (122) coupled to the requestor (104) and a target port (124) coupled to the target peripheral (112). The target port (124) breaks a single block access request from the requestor into multiple smaller access requests (2) for the target peripheral (112), each including a corresponding access address, in which the corresponding access addresses of the multiple smaller access requests access consecutive address locations of the target peripheral (112). The address mapping circuitry (110) maps (3) each of the corresponding access addresses of the multiple smaller access requests generated from the single block access request access to a same register of a first FIFO (130) of the target peripheral (112).

Anmelder

Firma

NXP USA, Inc.

Land

🇺🇸 USA