Nichtflüchtige Speichervorrichtung mit Cache-Speicheradresseninformationen Und/oder Eingangs-/ausgangskissenadresseninformationen und Verfahren zum Betrieb davon

Details

Veröffentlichungs-Nr.

EP4804190

Anmeldetag

5. Januar 2026

Veröffentlichung

9. September 2026

Rechtsraum

EP

IPC

G11C7/10, G11C16/26

Abstract

A nonvolatile memory device (11A) includes a memory cell array including a plurality of planes (PLN1-PLNn), a page buffer circuit (PBC) connected to the memory cell array through a plurality of bitlines and comprising at least one cache latch, and a plurality of input/output pads (DQ1-DQk) connected to the page buffer circuit through a plurality of data lines and configured to transmit data to and receive data from a memory controller (12A). A command set may include at least one of cache latch address information or input/output pad address information, and the nonvolatile memory device is configured to perform a readout operation or a write operation based on at least one of the cache latch address information or the input/output pad address information included in the command set.

Anmelder

Firma

Samsung Electronics Co., Ltd.

Land

🇰🇷 Südkorea

Fachgebiete