Halbleiterspeicheranordnung

Details

Veröffentlichungs-Nr.

EP4804750

Anmeldetag

8. Januar 2026

Veröffentlichung

9. September 2026

Rechtsraum

EP

IPC

H10B12/00, G11C11/4097

Abstract

A semiconductor memory device includes cell and peripheral structures. The cell structure includes first local bit lines extending in a vertical direction and spaced apart in a first horizontal direction, second local bit lines extending in the vertical direction and spaced apart from the first local bit lines in a second horizontal direction, a first global bit line extending in the first horizontal direction and electrically connected to the first local bit lines, and a second global bit line extending in the first horizontal direction and electrically connected to the second local bit lines. The peripheral circuit structure includes a peripheral circuit transistor, a first transistor electrically connected to the peripheral circuit transistor and the first global bit line, and a second transistor electrically connected to the peripheral circuit transistor and the second global bit line. The semiconductor memory device is configured to selectively turn on the first and second transistors in a complementary manner.

Anmelder

Firma

Samsung Electronics Co., Ltd.

Land

🇰🇷 Südkorea

Fachgebiete