Integrierte Schaltungsanordnung

Details

Veröffentlichungs-Nr.

EP4804759

Anmeldetag

18. Dezember 2025

Veröffentlichung

9. September 2026

Rechtsraum

EP

Abstract

An integrated circuit device includes at least one nanosheet, a pair of source/drain regions contacting the at least one nanosheet, a gate line between the pair of source/drain regions in a first horizontal direction and surrounding the at least one nanosheet, an insulating wall structure having a first sidewall contacting the pair of source/drain regions and facing the gate line, a gate dielectric film surrounding the gate line, and a pair of blocking insulating spacers arranged, in a plan view, in a gap area between the first sidewall and the gate line, in a second horizontal direction, and respectively contacting the pair of source/drain regions, wherein the pair of blocking insulating spacers are spaced apart from one another in the first horizontal direction in the gap area and each include a portion contacting the gate dielectric film and a portion contacting the first sidewall of the insulating wall structure.

Anmelder

Firma

Samsung Electronics Co., Ltd.

Land

🇰🇷 Südkorea