Tile-Programmoptimierung unter Verwendung von Sub-Tiles

Details

Veröffentlichungs-Nr.

EP4807535

Anmeldetag

12. März 2026

Veröffentlichung

16. September 2026

Rechtsraum

EP

IPC

G06F8/41

Abstract

Processors, systems, and techniques to cause a compiler to partition a tile of a tile program into a plurality of sub-tiles and perform tile program operations on the sub-tiles in a determined order. In at least one embodiment a compiler is to partition a tile of a tile program into a plurality of sub-tiles, wherein the compiler determines a size of the sub-tiles based, at least in part, on one or more accelerator hardware characteristics. The compiler is further to generate a plurality of instruction groups to be performed on corresponding sub-tiles of the plurality of sub-tiles, wherein the instruction groups are based, at least in part, on a tile operation to be performed on the tile of the tile program, determine an order to perform individual instruction groups of the plurality of instruction groups, and generate code to cause individual instruction groups to be performed in the determined order.

Anmelder

Firma

Nvidia Corporation

Land

🇺🇸 USA

Fachgebiete