Halbleiterspeicheranordnung mit Bandelement

Details

Veröffentlichungs-Nr.

EP4807740

Anmeldetag

11. Februar 2026

Veröffentlichung

16. September 2026

Rechtsraum

EP

Abstract

A memory device includes a memory cell array including memory cells arranged in a matrix, the memory cell array including a first memory cell (MC<p>) and a second memory cell (MC<p+1>) arranged in a column direction, a first bitline and a second bitline connected to the first memory cell (MC<p>) and the second memory cell (MC<p+1>), and a strap circuit (SC) provided between the first memory cell (MC<p>) and the second memory cell (MC<p+1>). Each of the first and second bitlines includes a first sub-bitline (BL<a>, BL'<a>) connected to the strap circuit (SC) and the first memory cell (MC<p>), a second sub-bitline (BL<b>, BL'<b>) connected to the strap circuit (SC) and the second memory cell (MC<p+1>), and a third sub-bitline (BL<c>, BL'<c>) connected to the strap circuit (SC) through the first sub-bitline (BL<a>, BL'<a>).

Anmelder

Firma

Samsung Electronics Co., Ltd.

Land

🇰🇷 Südkorea