Arrayorganisation in Dreidimensionalen Speicherschaltungen
Anmelder: Samsung Electronics Co., Ltd. 🇰🇷
Details
- Veröffentlichungs-Nr.
- EP4811358
- Anmeldetag
- 16. März 2026
- Veröffentlichung
- 23. September 2026
- Rechtsraum
- EP
Abstract
A system and a method for organizing a 3D memory circuit are disclosed. The 3D memory circuit includes a memory array and an activation circuit (235). The memory array is configured to be organized into N sections (340<1> to 340<N>). Each section has a row dimension K, a column dimension L, and a word line, WL, connected to L memory cells. The activation circuit (235) is configured to activate, in response to an activation, the WL to generate an activated WL. Each section includes a transfer circuit including a data switch and a select switch. The data switch is configured to route data between a local input/output, LIO, line and a global input/output, GIO, line. The select switch is configured to connect the LIO line to a bit line, BL, by a column select, CS, signal. The BL is connected to one of the L memory cells which is connected to the activated WL.
Anmelder
- Firma
- Samsung Electronics Co., Ltd.
- Land
- 🇰🇷 Südkorea
Südkoreanischer Elektronikkonzern und Teil der Samsung-Gruppe. Entwickelt und produziert Halbleiter, Speicherchips, Displays, Smartphones, Unterhaltungselektronik sowie Haushaltsgeräte für den globalen Markt.
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