Zellenhalbleiterbauelementstruktur mit Fusionierter Höhe und Verfahren zur Formung davon

Details

Veröffentlichungs-Nr.

EP4814778

Anmeldetag

23. März 2026

Veröffentlichung

30. September 2026

Rechtsraum

EP

IPC

G06F30/392

Abstract

A semiconductor cell architecture is disclosed including a merged-height cell (310), also known as a hyper or booster cell, having a cell height, CH, approximately one-and-one-half times that of a base unit cell (308) (1.5×CH). The base unit cell (308) follows a P/N/P/N vertical placement, while the merged-height cell (310) follows a P/N/N/P configuration. The merged-height cell (310) is vertically offset by about one-quarter cell height (0.25×CH) such that the nanosheet centers of NFET and PFET active regions in the merged-height cell (310) align with those in the base unit cell (308). This alignment allows direct abutment between base and merged-height cells (308, 310) without dummy filler regions, maintaining process limits on active-region jogs. The 1.5×CH architecture increases effective channel width (Weff) and drivability with reduced area penalty compared to conventional 2×CH merged-height cells (310). The merged-height cell architecture enables merged-height standard-cell libraries for sub-3 nm nodes, improving performance, area efficiency, and routing compatibility in advanced integrated-circuit design.

Anmelder

Firma

Samsung Electronics Co., Ltd.

Land

🇰🇷 Südkorea

Fachgebiete