Speichersystem

Details

Veröffentlichungs-Nr.

EP4814965

Anmeldetag

20. März 2026

Veröffentlichung

30. September 2026

Rechtsraum

EP

IPC

G11C11/16

Abstract

A memory system according to an embodiment includes: an STT-MRAM having a plurality of memory areas for storing data; and a memory controller configured to control a write and a read for each of the plurality of memory areas, wherein upon receiving a write request of data (S1), the memory controller selects any of a plurality of writes having different write times on the basis of predetermined information related to the data (S2) and writes the data to a corresponding one of the memory areas (S3, S4, S5).

Anmelder

Firma

AISIN CORPORATION

Land

🇯🇵 Japan

Fachgebiete