Ladungsschleuse, Halbleiterverarbeitungsvorrichtung und Waferausrichtungsverfahren

Details

Veröffentlichungs-Nr.

EP4815032

Anmeldetag

10. Dezember 2024

Veröffentlichung

3. Juli 2025

Rechtsraum

EP

IPC

H01L21/67, H01L21/00

Abstract

The present disclosure provides a load lock, semiconductor process equipment, and a wafer calibration method. The load lock includes: a chamber body, a first carrier plate, a second carrier plate, a driving mechanism, and a stop member. The first carrier plate and the second carrier plate are oppositely arranged inside the chamber body, and the first carrier plate and the second carrier plate are configured to carry wafers. The driving mechanism is connected to the second carrier plate and is configured to drive the second carrier plate to move toward or away from the first carrier plate. During a process in which the second carrier plate moves toward the first carrier plate, the first carrier plate and the second carrier plate are configured to clamp a wafer to a calibration position. The present disclosure may effectively improve wafer transfer efficiency.

Anmelder

Firma

Beijing NAURA Microelectronics Equipment Co., Ltd.

Land

🇨🇳 China

Fachgebiete