Phasenregelkreis und Betriebsverfahren dafür

Details

Veröffentlichungs-Nr.

EP4815312

Anmeldetag

22. Oktober 2025

Veröffentlichung

30. September 2026

Rechtsraum

EP

IPC

H03L7/093

Abstract

A phase locked loop is provided. The phase locked loop includes: a digitally controlled oscillator configured to generate an output clock according to a frequency control signal; a frequency divider circuit configured to generate a feedback clock by frequency dividing the output clock based on a first divide ratio value; a phase detection circuit configured to generate a phase difference signal according to a phase difference between the feedback clock and an externally provided reference clock; a loop filter circuit configured to generate a frequency control raw signal based on the phase difference signal; and a peaking suppression circuit configured to generate the frequency control signal by limiting a fluctuation range of the frequency control raw signal.

Anmelder

Firma

Samsung Electronics Co., Ltd.

Land

🇰🇷 Südkorea

Fachgebiete