Speicherinterne Rechenvorrichtung mit Analogkompensation und Verfahren

Details

Veröffentlichungs-Nr.

EP4819136

Anmeldetag

17. März 2026

Veröffentlichung

7. Oktober 2026

Rechtsraum

EP

IPC

G11C7/10, G11C13/00

Abstract

An in-memory computation device has: a word line activation circuit that receives input values and, in response, provides activation signals to word lines, as a function of the plurality of input values; a bias circuit that provides a corrected bias voltage to a bit line; and a memory array with memory cells couplable to the bit line and each to a word line. The memory cells are configured to be traversed by cell current that is a function of the bias voltage, an activation signal, and a computational weight. The bit line is configured to be traversed by a bit line current that is a function of a sum of the cell currents. A detection circuit provides, as a function of the bit line current, an output signal indicative of charge flowed in the bit line. The bias voltage is a function of a common bias signal and a calibration factor that is determined during a calibration step and is representative of an error between an actual computational result and an ideal computational result of the calibration step.

Anmelder

Firma

STMicroelectronics International N.V.

Land

🇨🇭 Schweiz

Fachgebiete