Speichervorrichtung und Betriebsverfahren dafür

Details

Veröffentlichungs-Nr.

EP4819137

Anmeldetag

17. März 2026

Veröffentlichung

7. Oktober 2026

Rechtsraum

EP

IPC

G11C7/12, G11C11/4091

Abstract

Provided is a memory device including a first sense amplification circuit (42) connected to a first input and output line pair (LIO, LIOB), a pre-charge circuit (44) connected to a second input and output line pair (GIO, GIOB), and a first switch circuit (43), wherein the pre-charge circuit (44) is configured to pre-charge the second input and output line pair (GIO, GIOB) at a pre-charge voltage after the first switch circuit (43) disconnects the first input and output line pair (LIO, LIOB) from the second input and output line pair (GIO, GIOB), and wherein the first switch circuit (43) is configured to connect the first input and output line pair (LIO, LIOB) and the second input and output line pair (GIO, GIOB) to deliver a voltage of the first input and output line pair (LIO, LIOB), which is amplified by the first sense amplification circuit (42), to the pre-charged second input and output line pair (GIO, GIOB) in a read operation.

Anmelder

Firma

Samsung Electronics Co., Ltd.

Land

🇰🇷 Südkorea

Fachgebiete