Musterungsverfahren zur Verwendung in der Halbleiterverarbeitung

Details

Veröffentlichungs-Nr.

EP4819199

Anmeldetag

1. April 2025

Veröffentlichung

7. Oktober 2026

Rechtsraum

EP

IPC

H01L21/3065, H01L21/308

Abstract

A target layer (25) that needs to be patterned is formed on a support substrate (26). An etch stop layer (27) and a first mask layer (28) are produced in that order on the target layer. According to embodiments of the invention, the first mask layer is patterned into a regular 2-dimensional array of openings (30). In a first directional etching step, the openings in the first mask layer are enlarged to thereby form a pattern of parallel first trenches (31) in the first mask layer (28). A second mask layer (32) is produced, possibly after thinning the patterned first mask layer. The second mask layer is patterned into the same regular array of openings (30) and thereafter the second mask layer is subjected to a second directional etching step, which enlarges the openings in the second mask layer to thereby form second parallel trenches (33) extending in a direction that crosses the direction of the first trenches,. The second directional etching also removes exposed portions of the first mask layer (28), so that the latter is eventually patterned into a pattern of pillars (34). After stripping the second mask layer (32) relative to said pillars, the pattern of pillars is transferred to the target layer (25).

Anmelder

Firma

Imec VZW

Land

🇧🇪 Belgien

Fachgebiete