Halbleiteranordnung
Anmelder: NXP USA, Inc. 🇺🇸
Details
- Veröffentlichungs-Nr.
- EP4819795
- Anmeldetag
- 31. März 2025
- Veröffentlichung
- 7. Oktober 2026
- Rechtsraum
- EP
- IPC
- H10D89/60, H02H9/04
Abstract
A semiconductor device comprising: a substrate; an epitaxial layer arranged on the surface of the substrate, the epitaxial layer comprising: a first p-doped region, a second p-doped region and a third p-doped region arranged laterally with the second p-doped region positioned between; a first n-doped region positioned between the first p-doped region and the second p-doped region; a second n-doped region positioned between the second p-doped region and the third p-doped region; a metal contact layer arranged above the epitaxial layer, the metal contact layer comprising: a signal connection comprising a first metal contact and a second metal contact; and a ground metal contact, wherein the first metal contact is connected to the first p-doped region, the ground metal contact is connected to the second p-doped region and the second metal contact is connected to the third p-doped region.
Anmelder
- Firma
- NXP USA, Inc.
- Land
- 🇺🇸 USA
US-amerikanische Gesellschaft des Halbleiterkonzerns NXP, die Chips und Halbleiterlösungen für Automobiltechnik, Kommunikation und Industrieelektronik entwickelt.
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