Arbeitszyklusüberwachungsschaltung

Details

Veröffentlichungs-Nr.

EP4822362

Anmeldetag

11. April 2025

Veröffentlichung

14. Oktober 2026

Rechtsraum

EP

IPC

G01R29/027, G01R31/317

Abstract

Aspects of this disclosure are directed to a duty cycle, monitoring circuit for receiving at an input, and monitoring a duty cycle of, a clock signal, and comprising: an averaging circuit, connected to the input and configured to average the received clock signal; a first and second comparators, configured to compare the averaged clock signal with upper and lower thresholds, and to output a firs and secondt error signal in response to the average clock signal exceeding the upper threshold, or being less that the second threshold; a divider circuit connected between a first node and a second node, and configured to generate the upper threshold and the lower threshold at respective first and second intermediate nodes; and a first detector circuit operably coupled between the first node and the input for providing, at the first node, a voltage dependent on a maximum of the received clock signal.

Anmelder

Firma

NXP USA, Inc.

Land

🇺🇸 USA

Fachgebiete