Speichervorrichtung zur Durchführung eines Chipauswahlsignaltrainingsbetriebs und Betriebsverfahren für Chipauswahlsignaltraining

Details

Veröffentlichungs-Nr.

EP4822700

Anmeldetag

20. März 2026

Veröffentlichung

14. Oktober 2026

Rechtsraum

EP

IPC

G11C29/02

Abstract

A memory device that performs a training operation on a chip select signal includes a clock divider receiving a clock signal from a host and dividing the clock signal to generate at least two internal clock signals, an internal clock selector receiving the at least two internal clock signals from the clock divider and selecting one of the at least two internal clock signals as a target internal clock signal to sample one of a high level or a low level of the chip select signal, and a sampler receiving the chip select signal from the host, receiving the target internal clock signal from the internal clock selector, and sampling the chip select signal using the target internal clock signal.

Anmelder

Firma

Samsung Electronics Co., Ltd.

Land

🇰🇷 Südkorea

Fachgebiete