Verfahren zur Herstellung einer Speicherstruktur für einen 3D-Nand-Flash-Speicher

Details

Veröffentlichungs-Nr.

EP4823268

Anmeldetag

7. April 2025

Veröffentlichung

14. Oktober 2026

Rechtsraum

EP

IPC

H10B43/27, H10D64/01

Abstract

According to an aspect, there is provided a method for forming a memory structure for a 3D NAND flash memory, the method comprising: forming a layer stack over a substrate, the layer stack comprising an alternating sequence of gate layers and inter-gate spacer layers; forming recessed areas in a sidewall surrounding a memory hole in the layer stack by laterally etching back the gate layers relative to the inter-gate spacer layers from the memory hole; forming an initial charge trap layer in each recessed area; depositing a tunneling oxide layer in the memory hole; depositing a channel layer on the tunneling oxide layer; forming an access trench in the layer stack; forming gate cavities in the layer stack by laterally etching back the gate layers from the access trench in a direction towards the memory hole, wherein the gate cavities expose the initial charge trap layers; oxidizing a portion of the initial charge trap layer in each gate cavity such that the oxidized portion forms a blocking oxide layer and a non-oxidized portion of the initial charge trap layer remains to form a final charge trap layer between the blocking oxide and the memory hole; and subsequent to forming the blocking oxide layer and the final charge trap layers, forming gate layers in the gate cavities by depositing gate material in the gate cavities via the access trench.

Anmelder

Firma

IMEC VZW

Land

🇧🇪 Belgien

Fachgebiete