Verfahren zur Herstellung einer Speicherstruktur für einen 3D-Nand-Flash-Speicher

EP4823269 14. Oktober 2026

Anmelder: IMEC VZW 🇧🇪

Details

Veröffentlichungs-Nr.
EP4823269
Anmeldetag
7. April 2025
Veröffentlichung
14. Oktober 2026
Rechtsraum
EP
IPC
H10B43/27, H10D64/01
Offizieller Volltext

Abstract

A method for forming a memory structure for a 3D NAND flash memory, the method comprising:forming a layer stack over a substrate, the layer stack comprising an alternating sequence of gate layers and inter-gate spacer layers;forming recessed areas in a sidewall surrounding a memory hole in the layer stack by laterally etching back the gate layers relative to the inter-gate spacer layers from the memory hole;forming a discrete blocking oxide layer in each recessed area, wherein a thickness of each blocking oxide layer in a lateral direction is less than a depth of each recessed area in the lateral direction;conformally depositing a continuous liner layer on exposed surfaces in the memory hole, wherein the liner layer covers the blocking oxide layer in each recessed area;depositing a continuous sacrificial layer on the liner layer;etching back the sacrificial layer such that the liner layer is exposed outside the recessed areas and discrete portions of the sacrificial layer remain in the recessed areas;removing exposed portions of the liner layer while using the discrete sacrificial layer portions as an etch mask such that discrete portions of the liner layer covered by the discrete sacrificial layer portions remain in the recessed areas;removing the discrete portions of the sacrificial layer in the recessed areas;forming a discrete charge trap layer in each recessed area, wherein each charge trap layer is deposited on the discrete liner layer portion remaining in each recessed area by a first area-selective deposition process while using the discrete liner layer portion as a seeding layer;subsequent to forming the charge trap layers, depositing a tunneling oxide layer in the memory hole; anddepositing a channel layer on the tunneling oxide layer.

Anmelder

Firma
IMEC VZW
Land
🇧🇪 Belgien
🇧🇪 imec

Imec ist ein belgisches Forschungszentrum mit Sitz in Leuven, das auf Nanoelektronik, Halbleitertechnologie und digitale Technologien spezialisiert ist.

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