Speichervorrichtung mit Breitem Io, Speichervorrichtung damit und Verfahren zum Betrieb davon

Details

Veröffentlichungs-Nr.

EP4826723

Anmeldetag

18. März 2026

Veröffentlichung

21. Oktober 2026

Rechtsraum

EP

IPC

G11C8/12, G11C7/10

Abstract

A memory device (30b) includes a plurality of planes (31, 32) and a control circuit. The plurality of planes (31, 32) may be included in a chip, and each of which may include a cell array and a page buffer. The control circuit, in a first mode, may enable or disable at least one first plane (31) among the plurality of planes (31, 32) based on a signal (nCE1) received through a first chip enable pad (P01) and output a signal (RnB1) that indicates a state of the at least one first plane (31) through a first ready/busy pad (P02). The control circuit may also enable or disable at least one second plane (32) among the plurality of planes (31, 32) based on a signal (nCE2) received through a second chip enable pad (P05) and output a signal (RnB2) that indicates a state of the at least one second plane (32) through a second ready/busy pad (P06).

Anmelder

Firma

Samsung Electronics Co., Ltd.

Land

🇰🇷 Südkorea

Fachgebiete