Arm Patente

A method of configuring an integrated-circuit system is disclosed, wherein the integrated-circuit system comprises a plurality of nodes of a network, the plurality of nodes comprising one or more processing nodes and a plurality of caching nodes. First-assignment data (301) is accessed that assigns each of the plurality of nodes to a respective local cache region of a plurality of local cache regions. Defect data is accessed that identifies one or more of the nodes as being defective. For a first node of the plurality of nodes that is identified as being defective by the defect data: a first local cache region is identified, to which the first node is assigned by the first assignment data; a distance metric is used to identify (304) a second node, not identified as being defective by the defect data, that is a closest node, out of a subset of the plurality of nodes, for the first local cache region, under the distance metric; and second assignment data is generated (305) in which the second node is assigned to the first local cache region.

A coherent data processing network includes request nodes and one or more caching nodes. A caching node is configured as a point of coherence for a range of addresses and is configured to receive requests from the request nodes for transfer of data associated with an address in the range of addresses and form a dependency chain from the requests in the memory of the caching node. When data associated with the address is received, by the caching node, it is forwarded, based on requests in the dependency chain to the plurality of request nodes. Responsive to an incoming snoop request for the address, the caching node may break the dependency chain for request nodes to which the data has not yet been forwarded.

A data processing network includes request nodes (RNs), home nodes (HNs) and local cache nodes (LCNs) coupled by an interconnect. The interconnect includes configuration logic programmable to define one or more local cache domains (LCDs). An LCD identifies a sub-network of the data processing network and associates a set of addresses with LCNs in the sub-network. For an RN in an LCD, the interconnect routes a data transfer request associated with an address in the set of addresses from the first RN to the LCN in the LCD associated with the address. For an address not in the set of addresses, the interconnect routes a data transfer request associated with the address to the HN associated with the address. LCDs may be configured at boot time.

An integrated-circuit apparatus (101) comprises a network of multi-channel routers (104; 301), each multi-channel router comprising one or more ingress network ports (306) and one or more egress network ports (306) for exchanging flits with one or more further multi-channel routers of the network. A multi-channel router (301) of the network comprises a plurality of upload device ports (302), each upload device port configured to receive upload flits from a respective device of the system, and a plurality of download device ports (302a), each configured to send download flits to a respective device of the system. The multi-channel router (301) further comprises a plurality of channel modules (304) configured to route flits from the upload device ports (302) and ingress network ports (306) to the download device ports (302a) and egress network ports (306). It is configured such that each of the channel modules (304) can receive flits from any ingress network port (306) associated with a respective channel of the plurality of channels and from only a respective subset of the upload device ports (302), particular to the respective channel module, and can selectively route flits to any egress network port (306) associated with the respective channel and to any of the plurality of download device ports (302a).

Direct data transfer in a data processing network is enabled by passing a transfer request, containing a source identifier and transaction identifier of an initiating request node, through two or more levels of cache hierarchy to a completer node. This enables the complete node to communicate directly with the initiating request node, bypassing intermediate cache nodes. The transfer request may be a request for direct read transfer, direct cache transfer, or direct write transfer, for example.

There is provided an apparatus, a system, a chip-containing product, a method, and a computer-readable medium. The apparatus comprises a requestor element configured to issue a memory access request, and control circuitry configured to receive the memory access request and to determine a request order in which to forward the received memory access request to a memory component relative to one or more further memory access requests. The control circuitry is configured, when determining the request order, to identify whether the memory access request is associated with a priority hint, and when the memory access request is associated with the priority hint, to prioritise the memory access request ahead of the at least one of the one or more further memory access requests in the request order.

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