Marks & Clerk GST

The present disclosure describes various aspects of implementing parallelizing secure monitor calls in an Arm architecture. In some aspects, an apparatus receives, from an application in a non-secure zone of the computing system, a Secure Monitor Call (SMC) requesting use of one or more trusted resources in a secure zone of the computing system. The apparatus enqueueing the SMC as an entry in a receive (RX) queue and evaluates SMC call information to schedule the SMC call for execution using the one or more trusted resources in the secure zone. Based on the execution of the SMC call, a scheduler receives a response to the scheduled SMC call. The apparatus enqueues the response to the SMC call in a transmit (TX) queue and sends a notification, to the application, indicating that the response to the SMC call is in the TX queue.

Methods, systems, and apparatus for cache data replacement in image processing. One of the methods includes maintaining in a cache image frame data blocks of an input image frame, the data blocks including pixel data corresponding to tiles forming an output image frame. The cache includes a plurality of lines each having a plurality of flags representing current and previous neighbor of a pixel in the pixel data on each of at least two levels based on portions of the output image frame. A flag is set that represents the current neighbor for cache lines that store data blocks that have one or more pixels that are neighbors of the pixel at each level. Which cache line to evict is determined based on the flags, where flags for lower levels and current neighbors have priority over flags of higher levels and previous neighbors.

This document describes technology for a runtime memory system that utilizes unpredictable multiplexing of memory bus lines. The technology dynamically reassigns data and/or address bus connections between a processor and its runtime memory during warm reset operations. The bus line assignments are made through a multiplexing mechanism-for example, data bus line from the processor may be reassigned to link with bus line at the runtime memory system interface. When a warm reset occurs, the physical mapping of memory locations changes due to this bus line reassignment. The system maintains standard memory operations while implementing this dynamic bus line configuration. Malicious software relying upon memory-resident exploit becomes inoperable after warm reset due to the changed physical memory topology created by the bus line reassignment process.

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Methods, systems, and apparatus for reducing latency of configuration of image sensor and image signal processor. A computing system can include a machine learning (ML) processing engine that can process denoising diffusion ML models for execution on statically compiled ML accelerators. The system can determine that a partitioned graph representation, which includes connected subgraphs that each represent at least one layer of the neural network of the ML model, forms a directed acyclic graph. The system can insert cache nodes in the graph representation, where each cache node corresponds to a respective subgraph and is configured to cache output of the respective subgraph. The system can generate an execution dataflow graph including a plurality of iterations of the partitioned graph representation, where, at one or more iterations during model inference operations, the execution dataflow graph uses inputs from cache nodes and excludes execution of subgraphs corresponding to the cache nodes.

Methods and systems for fine-tuning a machine-learning model using a fusion-frame representation are provided. Model weights associated with a layer of a machine-learning model are updated using a projection of a block diagonal matrix into a fusion frame, with each block of the block diagonal matrix projected onto a respective subspace of the fusion frame. This reduces the number of parameters that need to be handled during fine-tuning, reducing demand on processor and memory resources, as it is not necessary to fine-tune all the weights, only the elements of the block diagonal matrix. The use of fusion frames also enables targeting of particular parameters or parameter sets using the subspaces of the fusion frame. Furthermore, embodiments described herein show how the fusion frame implementation lends itself to parallelisation of calculations associated with each respective subspace.

Methods, systems, and computer storage media are provided for training generative neural network systems, such as Large Language Models (LLMs) or Vision-Language Models (VLMs), using multiple reward models. The process involves generating one or more output sequences from a training input sequence and processing these examples using a plurality of different reward models to generate respective reward values. These reward values are combined to obtain an aggregated reward, which may be calculated as a product of the values, a weighted geometric mean, or a Nash score. The generative neural network is trained using an objective function determined using the aggregated reward, such as a cross-entropy loss or a contrastive objective function, often utilizing log score differences between the system and a reference model. These techniques allow for multi-objective alignment and are adapted for implementation on parallel processing computer systems.

This document describes systems and techniques for delivering patch partitions to local function managers of a computing device. For example, a system includes a plurality of local function managers in a computing device, each of the local function managers is configured to identify an instance for execution of one or more patch partitions, each of the patch partitions including executable code to direct a local function and generate a patch request for the one or more patch partitions. A global function controller is configured to access a group of patch partitions including each of the one or more patch partitions for each of the plurality of local function managers and to respond to receipt of the patch request by delivering one or more requested patch partitions to the local function manager generating the patch request.

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for generating sequences of network outputs using a generative machine learning model following a learned generation order. In one aspect, a method comprises receiving a network input and generating a sequence of network outputs using a generative model, the generating comprising, at each of a plurality of iterations: identifying a set of candidate positions for the iteration; determining uncertainty scores for each of the set of candidate positions using an uncertainty scoring neural network; selecting a position of the sequence of network outputs from the set of candidate positions using the uncertainty scores; and generating the network output at the selected position of the sequence of network outputs using the generative model.

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