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This document describes technology for a runtime memory system that utilizes unpredictable multiplexing of memory bus lines. The technology dynamically reassigns data and/or address bus connections between a processor and its runtime memory during warm reset operations. The bus line assignments are made through a multiplexing mechanism-for example, data bus line from the processor may be reassigned to link with bus line at the runtime memory system interface. When a warm reset occurs, the physical mapping of memory locations changes due to this bus line reassignment. The system maintains standard memory operations while implementing this dynamic bus line configuration. Malicious software relying upon memory-resident exploit becomes inoperable after warm reset due to the changed physical memory topology created by the bus line reassignment process.

A first computing device is configured to receive an indication of subscription request to at least one data of a plurality of data fields of a media bridging protocol from a second computing device. The first computing device receives the indication of subscription request as specifying one or more types of messages that correspond to at least one of the plurality of data fields and that are to be sent via the bridging protocol to the second computing device. The first computing device is further configured to generate messages for the plurality of data fields and determine a subset of the generated messages that are associated with the subscribed data fields to be provided to the second computing device. The first computing device is further configured to provide the subset of messages to the second computing device via the bridging protocol.

Disclosed is an object storage system that can accept any number of write requests that add zero or more bytes to the end of the object. A write request may flush the data up to the current end of the object to make it durable and accessible for read operations. A write request may make the object permanently immutable.

The technology is generally for providing resilience to interconnect networks in large scale computing. Processing nodes of the network are arranged in reconfigurable pods that can contain large numbers of processing nodes. Processing nodes are grouped into building blocks of the pod, each building block may be contained within a physical computing rack. Processing nodes are interconnected via interconnect pathways that connect processing nodes to network switches. A building block's processing nodes communicate to network switches through regular communication pathways via the interconnect network. Additionally, a protection communication path is provided between a building block and the network. If a regular communication path is affected by a failure of a switch or interconnect link, the protection pathway is used to route the traffic affected by the failure without impacting the computing network. An electrical circuit switch is provided at the building block level to route data to the protection pathway.

An optical communication system includes a pair of transceivers and an optical circuit switch with multi-core fibers at each port that provides a communication bridge between the pair of transceivers. The transceivers each transmit a forward transmission signal through a first single-core fiber and receives a reverse transmission signal through a second single-core fiber. A fan-in/fan-out device can be positioned between the switch and each transceiver along an optical path. The fan-in/fan-out device is configured to couple the light or transmission signal transmitted through the single-core fiber with a core of a multi-core fiber. The multi-core fiber is further coupled to the port.

Methods, systems, and apparatus for reducing latency of configuration of image sensor and image signal processor. A computing system can include a machine learning (ML) processing engine that can process denoising diffusion ML models for execution on statically compiled ML accelerators. The system can determine that a partitioned graph representation, which includes connected subgraphs that each represent at least one layer of the neural network of the ML model, forms a directed acyclic graph. The system can insert cache nodes in the graph representation, where each cache node corresponds to a respective subgraph and is configured to cache output of the respective subgraph. The system can generate an execution dataflow graph including a plurality of iterations of the partitioned graph representation, where, at one or more iterations during model inference operations, the execution dataflow graph uses inputs from cache nodes and excludes execution of subgraphs corresponding to the cache nodes.

This document describes systems and techniques for delivering patch partitions to local function managers of a computing device. For example, a system includes a plurality of local function managers in a computing device, each of the local function managers is configured to identify an instance for execution of one or more patch partitions, each of the patch partitions including executable code to direct a local function and generate a patch request for the one or more patch partitions. A global function controller is configured to access a group of patch partitions including each of the one or more patch partitions for each of the plurality of local function managers and to respond to receipt of the patch request by delivering one or more requested patch partitions to the local function manager generating the patch request.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for performing a machine learning task on a network input to generate a network output using an attention neural network. The attention neural network includes a plurality of attention blocks arranged in a stack one after the other. One or more of the plurality of attention blocks are generalized residual attention blocks. Each generalized residual attention block includes one or more generalized residual blocks and an attention layer. The one or more generalized residual blocks includes a query generalized residual block.

A link layer architecture for D2D interconnections or communications. The architecture includes a self-contained D2D module that is capable of receiving data in multiple input bus protocols and transferring that data through a physical layer connection to another chiplet. The D2D module is a self-contained base block used to transfer data across dies. It includes a transmit (Tx) section/logic and a receive (Rx) section/logic. Each section/logic forms a building block that can be used to transfer data between dies or chiplets.

The present disclosure is generally directed to a modular busbar assembly that can be adjusted to fit varying rack power targets and connector interfaces, accommodating multiple connector geometries along one cost-effective assembly. The modular busbar assembly enables high power densities at powershelf regions by accommodating single- and double-pole connectors and connector contacts at various positions relative to the modular busbar assembly. The modular busbar assembly is customizable because the auxiliary busbar geometry may be altered independently from the primary busbar geometry.