Speicherschaltung mit Gleichzeitigen Schreibvorgängen und Verfahren dafür
Anmelder: NXP USA, Inc. 🇺🇸
Details
- Veröffentlichungs-Nr.
- EP3416169
- Aktenzeichen
- EP18159943
- Anmeldetag
- 5. März 2018
- Veröffentlichung
- 7. Juli 2021
- Erteilung
- 7. Juli 2021
- Rechtsraum
- EP
- IPC
- G11C7/10G06F12/02G11C11/406G11C16/10G11C11/16G11C11/22G11C8/14
Abstract
A memory circuit includes a plurality of memory tiles. Each memory tile in the plurality of memory tiles includes a plurality of bit cells and a control circuit coupled to the plurality of bit cells. The control circuit is configured to provide latched data to the plurality of bit cells during write operations. A first write control line is coupled to the control circuit in a first memory tile, and the first write control line is configured to initiate a first write operation in the first memory tile. And a second write control line is coupled to the control circuit in a second memory tile, and the second write control line configured to initiate a second write operation in the second memory tile. The second write operation may be initiated before the first write operation is completed.
Anmelder
- Firma
- NXP USA, Inc.
- Land
- 🇺🇸 USA
US-amerikanische Gesellschaft des Halbleiterkonzerns NXP, die Chips und Halbleiterlösungen für Automobiltechnik, Kommunikation und Industrieelektronik entwickelt.
1.545 Patente in unserer Datenbank
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Pomper, Till
NoneToulouse