Durch Digitalfrequenzteilerschaltung mit Ungerader Natürlicher Zahl und Verfahren

Details

Veröffentlichungs-Nr.

EP3503404

Aktenzeichen

EP17306893

Anmeldetag

22. Dezember 2017

Veröffentlichung

27. Oktober 2021

Erteilung

27. Oktober 2021

Rechtsraum

EP

IPC

H03K21/08H03K21/40

Abstract

The present application relates to a circuit of a frequency divider arranged to divide a frequency of an input clock signal by odd integer N and a method of operating the circuit. A shift register comprises a number of N+1 clock gating cells, which are connected in series to each other, and a shift logic. An input clock signal is fed into clock signal inputs of each one of the number of N+1 clock gating cells. The shift logic is configured to receive enable signals from a set of the number of N+1 clock gating cells and to generate a feedback signal, which is supplied to a gate enable input of the first one of the number of N+1 clock gating cells. A multiplexer is configured to receive at input ports N+1 gated clock signals and to output a rotation clock signal, which has a frequency of 2/N of the frequency of the input clock signal. A frequency generator is configured to receive the rotation clock signal and to generate an output clock signal having a frequency of 1/N.

Anmelder

Firma

NXP USA, Inc.

Land

🇺🇸 USA

Fachgebiete