Verfahren zur Bearbeitung eines Halbleiterbauelements mit Zwei Eng Beabstandeten Gates

Details

Veröffentlichungs-Nr.

EP3922596

Aktenzeichen

EP20179631

Anmeldetag

12. Juni 2020

Veröffentlichung

15. Dezember 2021

Rechtsraum

EP

IPC

B82Y10/00H01L29/06H01L29/41H01L29/423H01L29/66H01L29/76H01L27/06

Abstract

The present invention relates to a method for processing a semiconductor device with two closely spaced gates (40-45), wherein closely spaced means below a critical dimension (CD), typically less than 50 or less than 30 nm. The method comprises forming a template structure (1), wherein the template structure includes at least one sub-structure (between the gates 40, 41, 44, 45 and the gates 42 and 43) having a dimension less than the CD. The method further comprises forming a gate layer on and around the template structure. Then, the method comprises removing the part of the gate layer formed on the template structure, and patterning the remaining gate layer into a gate structure including the two gates. Further, the method comprises selectively removing the template structure, wherein the spacing between the two gates is defined by the removed sub-structure, having at the position between the two gates a dimension less than the critical dimension.

Anmelder

Firma

Imec VZW

Land

🇧🇪 Belgien

Fachgebiete