Taktkalibrierungsschaltung

Details

Veröffentlichungs-Nr.

EP4772957

Anmeldetag

10. Juli 2024

Veröffentlichung

6. März 2025

Rechtsraum

EP

IPC

G06F1/12

Abstract

Provided is a clock calibration circuit. The circuit includes: a first sampling circuit; and a second sampling circuit in series with the first sampling circuit; the first sampling circuit comprises: a phase-locked loop (PLL); a first duty cycle calibrator (DCC) connected in series with the PLL; a first phase interpolator (PI) connected in series with the first DCC; a first clock tree connected in series with the first PI; a first data serializer connected in series with the first clock tree; a first transmit driver connected in series with the first data serializer; a second data serializer connected in series with the first DCC; and a second transmit driver connected in series with the second data serializer; the PLL is configured to output a clock signal to drive the first data serializer to transmit data to be transmitted to the first transmit driver, and drive the second data serializer to transmit a feedforward clock signal to the second transmit driver; and the second transmit driver is configured to transmit the feedforward clock signal to a first receive driver in the second sampling circuit, to determine the feedforward clock signal as a sampling clock for the second sampling circuit.

Anmelder

Firma

Sanechips Technology Co., Ltd.

Land

🇨🇳 China

Fachgebiete