ams OSRAM Patente

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A low-dropout regulator comprises an output current branch (10) being arranged between a supply line (Vsupply) to provide a supply potential (VDD) and an output node (O) to provide a regulated output voltage (Vreg). The output current branch (10) comprises an output driver (20) to provide an output current (lout) at the output node (O). The output driver (20) has a control connection (G20) to apply a control voltage (Vc) to operate the output driver (20) with a different conductivity in dependence on the control voltage (Vc). The LDO comprises an input amplifier stage (30) to provide the control voltage (Vc) to the control connection (G20) of the output driver (20). The input amplifier stage (30) is configured to provide the control voltage (Vc) with a different slew rate in dependence on an increase or decrease of the output current (lout).

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In an embodiment a method for supplying energy wirelessly by means of RFID comprises the steps of sending by an RFID reader device (10) a request message (100) to at least one RFID tag device (20), receiving by the at least one RFID tag device (20) the request message (100), sending by the at least one RFID tag device (20) an answer message (110) to the RFID reader device (10) and changing by the at least one RFID tag device (20) its state into a high power mode, receiving by the RFID reader device (10) the answer message (110), sending by the RFID reader device (10) an energizing signal (120) having an unmodulated constant wave at a predefined frequency during an adjustable amount of time, receiving by the at least one RFID tag device (20) the energizing signal (120), converting said signal into energy and using the energy by the at least one RFID tag device, and changing by the at least one RFID tag device (20) its state into an RFID operation mode at the end of the adjustable amount of time.

The integrated imaging device comprises a substrate (1) with an integrated circuit (4), a cover (2), a cavity (6) enclosed between the substrate (1) and the cover (2), and a sensor (5) or an array of sensors (5) arranged in the cavity (6). A surface (11, 12) of the substrate (1) or the cover (2) opposite the cavity (6) has a structure (8) directing incident radiation. The surface structure (8) may be a plate zone or a Fresnel lens focusing infrared radiation and is preferably etched into the surface of the substrate or cover, respectively. At least one through-substrate via (9) may be provided to connecting the sensor (5) or array of sensors (5) electrically with a connection pad (10) on the surface (11) of the substrate (1) opposite the cavity (6).

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A circuit arrangement for an optical monitoring system comprises a driver circuit (DRV) which is configured to generate at least one driving signal for driving the light source (LS). A detector terminal (DT) is arranged for receiving a detector current (Id) from an optical detector (OD). A gain stage (GS) is connected at its input side to the driver circuit (DRV) for receiving the driving signal and generates a noise signal depending on the driving signal. A processing unit (PU) is configured to generate an output signal (SO) depending on the detector current (Id) and the noise signal.

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A charge pump circuit arrangement comprises a multitude of capacitors (110, 111, 112, 113) of a first and a second group controlled by non-overlapping clock pulses (CLK1, CLK2). The capacitors are partly realized in a semiconductor substrate including a deep well doping region and a high voltage doping region surrounded by the deep well doping region. Switches (324, 325) are connected to a pair of capacitors to control the deep well doping regions with signals (CTRL1, CTRL2) in phase with the corresponding clock signal (CLK1, CLK2).

An optical sensor arrangement for time-of-flight comprises a first and a second cavity (C1, C2) separated by an optical barrier (B) and covered by a cover arrangement (CA). An optical emitter (E) is arranged in the first cavity (C1), a measurement and a reference photodetector are arranged in the second cavity (C2). The cover arrangement (CA) comprises a plate (CP) and layers of material (LY) arranged on an inner main surface (SI) thereof The layers (LY) comprise an opaque coating (OC) with a first and second aperture (A1, A2) above the first cavity (C1), and with a third and fourth aperture (A3, A4) above the second cavity (C2). The measurement photodetector (PM) is configured to detect light entering the second cavity (C2) through the fourth aperture (A4). The second and the third aperture (A2, A3) establish a reference path for light from the emitter (E) to the reference photodetector (PR).

The sensor semiconductor device comprises a substrate (1) with a main surface (2), a sensor region (3) on or above the main surface, a coating layer (4) above the main surface, and a trench (5) formed in the coating layer around the sensor region. The trench provides drainage of a liquid from the coating layer.

A host device (10) may comprise an electrical power transmitting controller device (100), and an accessory device (20) may comprise an electrical power receiving controller device (200). After an identification and handshaking process to determine power requirements the power transmitting controller device (100) provides electrical power to the electrical power receiving controller device (200) to operate the accessory device. Coded communication data is transferred between the host device (10) and the accessory device (20) by a communication link. Power and communication are transferred over a single wire, such as an auxiliary pole (AUX) of a 3.5 mm jack interface (1020).

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A circuit arrangement comprises a first input node (11), a first output node (21), a sampling capacitor means (Cs, Cs1, Cs2) and a first switching means being switchable between a first switching state and a second switching state. The first switching means is coupled to the sampling capacitor means (Cs, Cs1, Cs2), the first input node (11) and the first output node (21) in such a way that the sampling capacitor means (Cs, Cs1, Cs2) is conductively connected to the first input node (11) and disconnected from the first output node (21) in the first switching state and the sampling capacitor means (Cs, Cs1, Cs2) is disconnected from the first input node (11) and conductively connected to the first output node (21) in the second switching state. A first charge-storing element is coupled via a second switching means to the first input node (11) in such a way that the charge-storing element is charged in the first switching state and discharged in the second switching state, thereby at least partly compensating current flow for charging the sampling capacitor means (Cs, Cs1, Cs2) in the first switching state.

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In one embodiment a low-dropout regulator comprises a first differential amplifier (Nmos1) to receive an input voltage (Vin), a power transistor (T1) coupled to the first differential input pair (Nmos1), the power transistor having an output (OUT) forming an output terminal of the low-dropout regulator to provide an output voltage (Vout) as a function of the input voltage (Vin), a second differential amplifier (Pmos1) coupled to the first differential amplifier (Nmos1), and a switching element (Mncut1, Mncut2) coupled between first and second differential amplifier (Nmos1, Pmos1), said switching element (Mncut1, Mncut2) being operated as a function of a feedback signal (Sfb) derived from the output voltage (Vout). The second differential amplifier (Pmos1) is complementary to the first differential amplifier (Nmos1). The low-dropout regulator is operated in one of two modes such that in a first mode the second differential amplifier (Pmos1) is enabled and in the second mode the first differential amplifier (Nmos1) is enabled and the second differential amplifier (Pmos1) is disabled by means of the switching element (Mncut1, Mncut2).

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An avalanche diode arrangement (10) comprises an avalanche diode (11) that is coupled to a first voltage terminal (16) and to a first node (13), an event detector (14) for detecting a trigger event of the avalanche diode (11) and being coupled to the first node (13), a quenching circuit (15) that is coupled to the first node (13), and a detection circuit (20) coupled to the first node (13). The detection circuit (20) is configured to provide a detection signal (SVC2) that depends on a value of a node voltage (SVA) at the first node (13).

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