GlobalFoundries U.S.

A system for developing a design in an advanced semiconductor-on-insulator processing technology includes a process design kit (PDK). A cell library in the PDK includes compact ancillary component cells placeable adjacent a functional block in a design layout. Some cells contain pairs of ancillary components including: a first ancillary component (e.g., a substrate diode) in a first hybrid area; a second ancillary component (e.g., a zero bias tap, a bias tap, or a signal antenna) in a second hybrid area; a first semiconductor-on-insulator area between the first and second hybrid areas and including less than five gate structures; and a second semiconductor-on-insulator area between the second hybrid area and functional block. Another cell contains a stand-alone signal antenna component and is placeable in the design layout between sections of a stacked memory-type functional block without requiring supporting cells. An IC structure can be manufactured according to such a design layout.

Structures for an optical switch and methods of forming such structures. The structure comprises a Mach-Zehnder interferometer including a first arm, a second arm, a first waveguide core section coupled to the first arm, and a second waveguide core section coupled to the second arm. The structure further comprises a first ring resonator and a second ring resonator. The first ring resonator is positioned between the first waveguide core section and the second ring resonator, and the second ring resonator is positioned between the second waveguide core section and the first ring resonator.

The present disclosure relates to semiconductor structures and, more particularly, to a contact strap extending to a common source/drain region of adjacent gate structures and methods of manufacture. The structure includes: a first gate structure; a second gate structure adjacent to the first gate structure; a common diffusion region to the first gate structure and the second gate structure; a trench lined with insulator material; and a contact strap extending within the trench and connecting to the common diffusion region.

The present disclosure relates to semiconductor structures and, more particularly, to a lateral heterojunction bipolar transistor (HBT) and methods of manufacture. The structure includes: a buried extrinsic base (20) within a semiconductor material (18); an intrinsic base (24) over and in electrical contact with the extrinsic base (20); an emitter (12) having a semiconductor material with a single crystalline orientation, the emitter being (12) above the intrinsic base (24) and comprising a faceted sidewall (12a); a collector (16) having the semiconductor material with the single crystalline orientation, the collector (16) being above the intrinsic base (24) and comprising a faceted sidewall (16a); and a spacer (14) between the emitter and the collector.

Structures for a Mach-Zehnder interferometer and methods of forming a structure for a Mach-Zehnder interferometer. The structure comprises a Mach-Zehnder interferometer including a first directional coupler, a second directional coupler, a first delay arm between the first and second directional couplers, and a second delay arm between the first and second directional couplers. The first delay arm includes a portion with a U-shape that surrounds a pocket, and the second delay arm includes a portion with a U-shape that extends into the pocket.

The present disclosure relates to an optical fiber positioning device and, more particularly, to an optical fiber positioning device and a method for attaching a fiber optic array to a photonic integrated circuit (PIC). The structure includes: a body having a first end and a second end; a dome shaped indicator provided on the body; a first positioning mark associated with the dome shaped indicator; and a second positioning mark under the first positioning mark and associated with the dome shaped indicator.

Disclosed are embodiments of structure including: a chip with an embedded magnetic random access memory (eMRAM) or other on-chip component susceptible to magnetic field-induced performance degradation; and magnetic shield(s) for protecting the chip. In some embodiments, a magnetic shield includes abutting magnetic layers having different magnetic properties. In other embodiments, a magnetic shield includes abutting magnetic layers (of the same or different magnetic materials) having offset patterns of openings (e.g., through-holes or mesh). In any case, the chip can be mounted on a board and contained in a package. Such magnetic shields can be located on the package (opposite the board) and/or on the board (opposite the chip) depending upon the expected location of a potentially adverse magnetic field.

The disclosure provides a vertical bipolar transistor with an emitter contact (146) wider than an emitter terminal (114, 148), and related methods. A structure of the disclosure includes an emitter contact (146) within an inter-level dielectric (140) layer and on an emitter terminal (114, 148) of a bipolar transistor (100), wherein a horizontal width of the emitter contact (146) is greater than a horizontal width of the emitter terminal (114, 148) thereunder.

The present disclosure relates to semiconductor structures and, more particularly, to high-electron-mobility transistors with field plates and methods of manufacture. The structure includes: a gate structure on a semiconductor substrate; a passivation layer adjacent to the gate structure and above the semiconductor substrate; an insulator material over the passivation layer; and a field plate comprising a first portion contacting the passivation layer and a second portion being separated from the passivation layer by the insulator material.

Structures for a photonic component and methods of forming a structure for a photonic component. The photonic structure comprises a semiconductor substrate, a first waveguide core including a first plurality of segments, and a second waveguide core including a second plurality of segments. The second plurality of segments are positioned between the first plurality of segments and the substrate.