GlobalFoundries U.S.

Disclosed are embodiments of structure including: a chip with an embedded magnetic random access memory (eMRAM) or other on-chip component susceptible to magnetic field-induced performance degradation; and magnetic shield(s) for protecting the chip. In some embodiments, a magnetic shield includes abutting magnetic layers having different magnetic properties. In other embodiments, a magnetic shield includes abutting magnetic layers (of the same or different magnetic materials) having offset patterns of openings (e.g., through-holes or mesh). In any case, the chip can be mounted on a board and contained in a package. Such magnetic shields can be located on the package (opposite the board) and/or on the board (opposite the chip) depending upon the expected location of a potentially adverse magnetic field.

The present disclosure relates to semiconductor structures and, more particularly, to high-electron-mobility transistors with field plates and methods of manufacture. The structure includes: a gate structure on a semiconductor substrate; a passivation layer adjacent to the gate structure and above the semiconductor substrate; an insulator material over the passivation layer; and a field plate comprising a first portion contacting the passivation layer and a second portion being separated from the passivation layer by the insulator material.

The disclosure provides a vertical bipolar transistor with an emitter contact (146) wider than an emitter terminal (114, 148), and related methods. A structure of the disclosure includes an emitter contact (146) within an inter-level dielectric (140) layer and on an emitter terminal (114, 148) of a bipolar transistor (100), wherein a horizontal width of the emitter contact (146) is greater than a horizontal width of the emitter terminal (114, 148) thereunder.

Structures for a photonic component and methods of forming a structure for a photonic component. The photonic structure comprises a semiconductor substrate, a first waveguide core including a first plurality of segments, and a second waveguide core including a second plurality of segments. The second plurality of segments are positioned between the first plurality of segments and the substrate.

Structures for a phase shifter and methods of forming such structures. The structure comprises a first layer comprising a first electro-optic material, a second layer comprising a second electro-optic material, and a third layer between the first layer and the second layer. The third layer comprises a dielectric material that is an electrical insulator. A waveguide core is positioned on a portion of the first layer.

A bit cell (BC) includes: a variable resistor and a first transistor connected in series between two end nodes; and a second transistor also connected between the two end nodes. Gates of the first and second transistors are connected to first and second word lines (WLs), respectively, for a row. A circuit includes an array of BCs. In each column, BCs are connected in a stack between a sense amplifier (SA) and footer device (FD). During a read operation, FDs connect the stacks to ground. Additionally, first and second WL voltages on first and second WLs for each row are such that, for any selected row, first transistors of BCs are on and second transistors are off and, for any unselected row, first transistors of BCs are off and second transistors are on. SAs compare sense currents from the stacks to a mid-level reference current to concurrently compute majority functions.

A gain cell memory device includes a semiconductor device layer of a silicon on insulator (SOI) substrate comprising an active region, a storage transistor over the active region of the semiconductor device layer, an isolation structure between a gate electrode of the storage transistor and a source/drain region adjacent to the storage transistor, the isolation structure extending through the active region such that a first portion of the active region is isolated from a second portion of the active region, and a capacitor coupled to the storage transistor. A bottom plate of the capacitor comprises the first portion of the active region, a gate dielectric layer of the storage transistor is an insulator of the capacitor, and a top plate of the capacitor comprises the gate electrode of the storage transistor and a metal structure over the gate electrode.

Structures for a high-electron-mobility transistor and methods of forming such structures. The structure comprises a layer stack including an active region, and a dielectric layer on the active region of the layer stack. The active region has a perimeter. The dielectric layer includes an opening and portions between the opening and the perimeter of the active region. The structure further comprises a source/drain region inside the opening in the dielectric layer.

The present disclosure relates to heterojunction bipolar transistors with a common extrinsic base, and methods of manufacture. The structure includes: a first transistor (100) having an intrinsic base (14a), an extrinsic base (12a) and an emitter (32a); and a second transistor (200) having an intrinsic base (14b), an extrinsic base (12b) and an emitter (32b). The extrinsic base (12a) of the first transistor and the extrinsic base (12b) of the second transistor have a common extrinsic base region (12a, b, c) with a first dopant type for the first transistor and a second opposite dopant type for the second transistor.

Embodiments of the disclosure provide a circuit structure and method with a resistor for reducing a discharged pad voltage. A structure of the disclosure includes a resistor having a first end connected to a pad and a second end opposite the first end. A trigger circuit is connected between the pad and ground. A discharge circuit is connected between the second end of the resistor and ground. The discharge circuit is connected to an output node of the trigger circuit.