Lambacher, Michael

The present disclosure relates to semiconductor structures and, more particularly, to a contact strap extending to a common source/drain region of adjacent gate structures and methods of manufacture. The structure includes: a first gate structure; a second gate structure adjacent to the first gate structure; a common diffusion region to the first gate structure and the second gate structure; a trench lined with insulator material; and a contact strap extending within the trench and connecting to the common diffusion region.

The present disclosure relates to semiconductor structures and, more particularly, to a lateral heterojunction bipolar transistor (HBT) and methods of manufacture. The structure includes: a buried extrinsic base (20) within a semiconductor material (18); an intrinsic base (24) over and in electrical contact with the extrinsic base (20); an emitter (12) having a semiconductor material with a single crystalline orientation, the emitter being (12) above the intrinsic base (24) and comprising a faceted sidewall (12a); a collector (16) having the semiconductor material with the single crystalline orientation, the collector (16) being above the intrinsic base (24) and comprising a faceted sidewall (16a); and a spacer (14) between the emitter and the collector.

Structures for a Mach-Zehnder interferometer and methods of forming a structure for a Mach-Zehnder interferometer. The structure comprises a Mach-Zehnder interferometer including a first directional coupler, a second directional coupler, a first delay arm between the first and second directional couplers, and a second delay arm between the first and second directional couplers. The first delay arm includes a portion with a U-shape that surrounds a pocket, and the second delay arm includes a portion with a U-shape that extends into the pocket.

The present disclosure relates to an optical fiber positioning device and, more particularly, to an optical fiber positioning device and a method for attaching a fiber optic array to a photonic integrated circuit (PIC). The structure includes: a body having a first end and a second end; a dome shaped indicator provided on the body; a first positioning mark associated with the dome shaped indicator; and a second positioning mark under the first positioning mark and associated with the dome shaped indicator.

Structures for a photonic component and methods of forming a structure for a photonic component. The photonic structure comprises a semiconductor substrate, a first waveguide core including a first plurality of segments, and a second waveguide core including a second plurality of segments. The second plurality of segments are positioned between the first plurality of segments and the substrate.

The present disclosure relates to semiconductor structures and, more particularly, to body contacted transistors and methods of manufacture. The structure includes: an active gate structure on a semiconductor substrate; at least one body contact extending through the active gate structure and connecting to a body region that contains a channel of the active gate which is under the active gate structure; and insulator material isolating the at least one body contact from the active gate structure.

Structures for a memory device and methods of forming a structure for a memory device. The structure (10) comprises a first transistor (48) including a first gate structure (18) and a first source/drain region (31, 32), a second transistor (50) including a second gate structure (20) and a second source/drain region (31, 32), and a capacitor including a first capacitor plate (43) directly coupled to the first source/drain region, a second capacitor plate (40), and a capacitor dielectric layer (38) between the first capacitor plate and the second capacitor plate.

The present disclosure relates to semiconductor structures and, more particularly, to diode triggered silicon controlled rectifiers and methods of manufacture. The structure includes: a vertical silicon controlled rectifier (SCR) having a doped semiconductor material region over a semiconductor substrate; and at least one vertical triggering diode electrically connected to the SCR in series, and having a doped semiconductor material region over a doped region in the semiconductor substrate.

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …