Imagination Technologies Patente

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

<div notation="docdba" type="abstract" xml:lang="en"><p>A synchronisation symbol detector that comprises two correlation modules and a comparison module. The first correlation module performs one or more correlations between the input signal and a down-converted version of the input signal and generates a first correlation metric from the one or more first correlations. The second correlation module performs one or more second correlations between the input signal and an up-converted version of the input signal and generates a second correlation metric from the one or more second correlations. The comparison module is configured to compare the first correlation metric and the second correlation metric and determine whether the input signal comprises a synchronisation symbol based on the comparison.</p></div>

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

Hierarchical methods for selecting fixed point number formats with reduced mantissa bit lengths for representing values input to, and/or output, from, the layers of a DNN. The methods begin with one or more initial fixed point number formats for each layer. The layers are divided into subsets of layers and the mantissa bit lengths of the fixed point number formats are iteratively reduced from the initial fixed point number formats on a per subset basis. If a reduction causes the output error of the DNN to exceed an error threshold, then the reduction is discarded, and no more reductions are made to the layers of the subset. Otherwise a further reduction is made to the fixed point number formats for the layers in that subset. Once no further reductions can be made to any of the subsets the method is repeated for continually increasing numbers of subsets until a predetermined number of layers per subset is achieved.

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

A hardware monitor arranged to assess performance of a hardware design for an integrated circuit to complete a task. The hardware monitor includes monitoring and counting logic configured to count a number of cycles between start and completion of the symbolic task in the hardware design; and property evaluation logic configured to evaluate one or more formal properties related to the counted number of cycles to assess the performance of the hardware design in completing the symbolic task. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design meets a desired performance goal and/or to exhaustively identify a performance metric (e.g. best case and/or worst case performance) with respect to completion of the task.

Data compression (and corresponding decompression) is used to compress blocks of data values involving processes including one or more of colour decorrelation, spatial decorrelation, entropy encoding and packing. The entropy encoding generates encoded data values which have variable sizes (in terms of the number of bits). The entropy encoding uses size indications for respective sets of data values to indicate the number of bits used for the encoded data values of the set. The size indications allow the encoded data values to be parsed quickly (e.g. in parallel).

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

Apparatuses, methods, apparatuses, and systems for of selectively deactivating portions of a receiver based on dynamic measurements are disclosed. One embodiment of a method includes receiving, by the receiver, a wireless signal, identifying a packet within the wireless signal during a preamble of the packet, determining whether the packet cannot be decoded with a reliability greater than a threshold during the preamble of the packet, and powering down at least a portion of the receiver for at least an expected duration of the packet after determining that the packet cannot be decoded with the reliability greater than the threshold during the preamble of the packet.

Zusammenfassung wird geladen …

An apparatus configured to identify a set of M output memory addresses from a larger set of N input memory addresses containing at least one non-unique memory address, the apparatus comprising: a comparator block configured to perform comparisons of memory addresses from a set of N input memory addresses to generate a binary classification dataset that identifies a subset of addresses from the set of input addresses, where each address in the subset identified by the binary classification dataset is unique within that subset; a plurality of combination logic units, each combination logic unit being configured to: receive a predetermined selection of bits of the binary classification dataset; and sort its received predetermined selection of bits into an intermediary binary string in which the bits are ordered into a first group identifying addresses belonging to the identified subset, and a second group identifying addresses not belonging to the identified subset; and output generating logic configured to select between bits belonging to different intermediary binary strings to generate a binary output identifying a set of output memory addresses containing at least one address in the identified subset.

Zusammenfassung wird geladen …