NXP Semiconductors

Described is a system, and method for monitoring a digital signature, comprising: generating keypairs K_st, each comprising an OTS public key and a seed-derived OTS private key, each associated with an index st; generating a binary tree, a root of which corresponds to a master public key and leaf-nodes of which to keypairs K_st, storing the seed, master public key and index st in a first processor and multiple nodes in a second processor, receiving a digital signature request; in response: downloading the seed, master public key, and index st, selecting the keypair K_st associated with the index st,computing an authentication path for K_st using the multiple nodes, creating a digital signature comprising the authentication path, deleting at least one node belonging to the authentication path, replacing the index st with st+1 in the first processor,and verifying the validity of the digital signature.

A method includes providing a circuit substrate including an active surface including one or more protrusions formed from a first material with a first melt temperature; coating each of the one or more protrusions with a second material having a second melt temperature that is less than the first melt temperature; and pressing a semiconductor device die onto the circuit substrate to form a circuit assembly, where the die includes one or more cavities aligned with the protrusions. Each die is plated with a third material having a third melt temperature that is greater than the second melt temperature. The method includes heating the circuit assembly at a selected temperature that is greater than or equal to the second melt temperature and that is less than the first and third melt temperatures to reflow the second material to form an intermetallic connection between the substrate and the die.

A method comprising, providing a plurality of first semiconductor dies on a surface of a carrier in a first region. Providing a second semiconductor die on the carrier in a second region. Etching a trench between each of the semiconductor dies, each trench extends into the carrier to a depth. Mounting a grinding foil on the carrier to attach each semiconductor die to the grinding foil. Back grinding a surface of the carrier to the depth. Applying a carrier foil to the back-grinded surface of the carrier. Either modifying the grinding foil or the carrier foil in a region aligned with the first region or use a de-taping module to press the grinding foil to the carrier foil. Then releasing, the plurality of first semiconductor dies from the grinding foil. The plurality of first semiconductor dies release from the grinding foil on removal of the grinding foil from the carrier.

A capacitor cell includes two capacitor circuits and two cell nodes, where each capacitor circuit is located in a path between a circuit node of the cell and a respective cell node. The capacitor cell includes enabling transistors that are made conductive to enable the capacitance of the cell to be utilized by a circuit such as an oscillator for frequency control by an enable signal that has a voltage range between a low supply voltage and a high supply voltage. One of the enabling transistors is coupled between the cell nodes. Each of two enabling transistors includes a first current terminal coupled in a path to a respective cell node. The second current terminals of the two enabling transistors are biased at a bias voltage that is less than the high supply voltage when the enable signal is not asserted.

A distributed coherent radar, DCR (100), is disclosed that maintains synchronization between clocks of radars (102, 104). A determination is made that a first radar (102) is being started up or a mode of the first radar is being changed. A measured temperature indicative of a temperature of a digitally controlled crystal oscillator, DCXO (118,130), of the first radar is obtained based on the determination. A DCXO control setting of the DCXO of the first radar is identified based on the temperature to reduce a frequency drift of the DCXO of the first radar and frequency drift difference between the DCXO of the first radar and DCXO of a second radar (104). The DCXO of the first radar is adjusted with the DCXO control setting. The DCXO of the first radar and DCXO of the second radar indicates timing for clocks of respective radars and the adjustment maintains the synchronization between the clocks.

A transcendental math accelerator including a barrel shifter, a polynomial coefficient table (PCT), a polynomial interpolator, a normalization shifter, a result exponent table (RET), and exponent and sign logic (ESL). The barrel shifter shifts the input mantissa based on a specified function and the input exponent into a polynomial coefficient table index (PCTI) and an interpolation index. The PCT selects a coefficient set using the specified function and the PCTI. The polynomial interpolator calculates a preliminary output mantissa according to a polynomial equation using the coefficient set and the interpolator index. The normalization shifter shifts the output mantissa for a normalized floating-point format. The RET selects an exponent based on the function, the input exponent, and the PCTI. The ESL determines the output sign using the input sign and the function, and determines the output exponent based on the input exponent, the result exponent, and any shifts by the normalization shifter.

A controller area network, CAN, transceiver comprising: CAN bus pins for connecting to a CAN bus; a TXD pin for receiving transmission data from a controller associated with the CAN transceiver; a driver circuit configured to receive the transmission data from the TXD pin and selectively apply a differential voltage signal to the CAN bus pins to selectively assert a dominant bit on the CAN bus in response to the transmission data; and a dominant control circuit configured to: detect assertion of a dominant bit on the CAN bus by sensing a current associated with the differential voltage signal applied by the driver circuit to at least one of the CAN bus pins; and enable a safe mode by inhibiting a flow of the current in response to detecting erroneous assertion of the dominant bit.

A multi-level panel level package substrate is formed with a compact vertical balun for converting between single-ended and differential-ended signals, where the vertical balun includes a first non-phase-shifting conductive balun path element having one or more vertically aligned conductive structures formed in at least two package layers and connected between a first differential-ended signal balun node and a single-ended signal balun node; a second phase-shifting conductive balun path element having a plurality of conductive structures formed in at least two package layers and connected between a second differential-ended signal balun node and the single-ended signal balun node; and a single-ended contact element integrally formed with the single-ended signal balun node at a package layer location where the first non-phase-shifting conductive balun path element is directly, electrically connected to the second phase-shifting conductive balun path element.

A system comprises: at least one processor core (110) supporting a virtual machine (120); an interface (150) configured for communication between the processor core (110) and a memory (160); a resource domain controller, RDC (130), configured to control access to the memory (160); and a secure enclave (140); wherein the resource domain controller, RDC (130), is configured by the secure enclave (140). A method for controlling access to a memory (160) and/or a device (170) assigned to a virtual machine (120) comprises: allocating, by a secure enclave (140), at least one memory region of the memory (160) to the virtual machine (120); assigning, by the secure enclave (140), a domain identifier to a processor core (110) supporting the virtual machine (120) and/or the device (170); and providing to the resource domain controller (130), by the secure enclave (140), the domain identifier and information identifying said at least one memory region allocated to the virtual machine (120).

The proposed method improves dynamic range utilization of the ADC unit by adjusting the amplifier gain and a reference gain level used to compensate the amplifier gain adjustment, based on a saturation status of the ADC unit. An update of the reference gain level is performed according to the gain change of the analog amplifier of the received signal and the recent ADCs saturation status. This provides a technical advantage by ensuring that the decoded signal remains steady when the amplifier gain is adjusted, thus maintaining signal integrity. This may help to achieve a more or less steady output in all circumstances. Resulting therefrom, the signal to be decoded is kept constant. This may be useful, when the received signal is strong and the ADC unit is saturated despite adaptation of gain.