NXP USA

The present disclosure relates to a package assembly including an integrated circuit die having standoff structures and associated methods of die attach and fabrication. The package may include an integrated circuit die having standoff structures disposed on a bottom surface of the integrated circuit die, a die pad structure on which the integrated circuit die is disposed, and die attach material disposed between the integrated circuit die and the die pad structure. The standoff structures can include metallic ink. The standoff structures may contact an upper surface of the die pad structure. The die attach material may attach the integrated circuit die to the die pad structure.

A Doherty power amplifier circuit includes a first impedance circuit (230), a second impedance circuit (260), and a third impedance circuit (276). The first impedance circuit is coupled between a carrier amplifier and a combining node (246) that is connected to an output terminal (206). The second impedance circuit (260) includes an input coupled to an output of a peaking amplifier and includes an output. The third impedance circuit (276) is coupled between the output of the second impedance circuit (260)and the combining node (246). The first impedance circuit (230) provides a first impedance and the second and third impedance circuits (260, 276) provide a second impedance to the combining node (246) to produce an output impedance configured to match a load impedance. The first impedance circuit (230) provides a ninety-degree phase offset and the second and third impedance circuits (260, 276) provide a zero-degree phase offset.

Aspects of this disclosure are directed to a duty cycle, monitoring circuit for receiving at an input, and monitoring a duty cycle of, a clock signal, and comprising: an averaging circuit, connected to the input and configured to average the received clock signal; a first and second comparators, configured to compare the averaged clock signal with upper and lower thresholds, and to output a firs and secondt error signal in response to the average clock signal exceeding the upper threshold, or being less that the second threshold; a divider circuit connected between a first node and a second node, and configured to generate the upper threshold and the lower threshold at respective first and second intermediate nodes; and a first detector circuit operably coupled between the first node and the input for providing, at the first node, a voltage dependent on a maximum of the received clock signal.

According to the present disclosure, there is provided an air-filled waveguide, AWG, assembly for use with a launcher-in-package semiconductor device, and comprising a stack of; a first laminate structure configured to be coupled to a semiconductor die, and having a first aperture therethrough; a second laminate structure affixed to the first laminate structure, having a second aperture, aligned with the first aperture, therethrough, and having a main AWG there-along; and a third laminate structure affixed to the second laminate structure, and having at least one bridging AWG there-along; wherein the AWG assembly is arranged to guide a microwave or millimetre-wave signal between the semiconductor die and the AWG in the second laminate, through the first and second aperture and along the bridging AWG.

The present disclosure relates to a sensor device comprising a sensor substrate, a sensor capacitor, a first sensor contact element, and a second sensor contact element, wherein the sensor capacitor is arranged on a surface, referred to as the first top surface, of the sensor substrate, wherein the sensor capacitor comprises a first sensor electrode and a second sensor electrode, wherein the second sensor electrode is arranged between the first sensor electrode and the first top surface of the sensor substrate such that a sensor cavity is provided between the two sensor electrodes, wherein both sensor contact elements are arranged on another surface, referred to as the first bottom surface, of the sensor substrate, wherein a first electrical interconnection extends through the sensor substrate from the first sensor electrode to the first sensor contact element, and wherein a second electrical interconnection extends through the sensor substrate from the second sensor electrode to the second sensor contact element.

A semiconductor device comprising: a substrate; an epitaxial layer arranged on the surface of the substrate, the epitaxial layer comprising: a first p-doped region, a second p-doped region and a third p-doped region arranged laterally with the second p-doped region positioned between; a first n-doped region positioned between the first p-doped region and the second p-doped region; a second n-doped region positioned between the second p-doped region and the third p-doped region; a metal contact layer arranged above the epitaxial layer, the metal contact layer comprising: a signal connection comprising a first metal contact and a second metal contact; and a ground metal contact, wherein the first metal contact is connected to the first p-doped region, the ground metal contact is connected to the second p-doped region and the second metal contact is connected to the third p-doped region.

The present disclosure relates to a circuit for a transmitter, the circuit comprising: a first supply terminal, a second supply terminal, a first output terminal, a second output terminal, wherein a first circuit string extends from the first supply terminal to a first node of the circuit, wherein a first transistor is integrated in the first circuit string, wherein a second circuit string extends from the second supply terminal to a second node of the circuit, wherein a second transistor is integrated in the second circuit string, wherein a third circuit string extends from the second supply terminal to the first node of the circuit, wherein a third transistor is integrated in the third circuit string, wherein a fourth circuit string extends from the first supply terminal to the second node of the circuit, wherein a second transistor is integrated in the second circuit string, wherein a first connection string extends from the first node to the first output terminal, wherein a first resistor is integrated into the first connection string, and wherein a second connection string extends from the second node to the second output terminal, wherein a second resistor is integrated into the second connection string.

A data processing system (100) includes a requestor (104), a split transaction interconnect (102), and address mapping circuitry (110). The requestor (104) issues block access requests (1) to a target peripheral (112). The target peripheral (112) includes a set of first-in first-out structures (FIFOs) (130) which buffer incoming or outgoing data. The split transaction interconnect (102) has a requestor port (122) coupled to the requestor (104) and a target port (124) coupled to the target peripheral (112). The target port (124) breaks a single block access request from the requestor into multiple smaller access requests (2) for the target peripheral (112), each including a corresponding access address, in which the corresponding access addresses of the multiple smaller access requests access consecutive address locations of the target peripheral (112). The address mapping circuitry (110) maps (3) each of the corresponding access addresses of the multiple smaller access requests generated from the single block access request access to a same register of a first FIFO (130) of the target peripheral (112).

One example discloses a power regulator, including: a power output node configured to be coupled to a high-side of a load; a load ground node configured to be coupled to a low-side of the load; a negative feedback node (Fbm) configured to form a negative feedback path when coupled to the low-side of the load; a controller configured to regulate voltages at the power output node and the load ground node in response to a voltage on the negative feedback path; a current source configured to inject a current at the negative feedback node (Fbm); and a detector circuit configured to monitor a voltage (VFbm) at the negative feedback node (Fbm); wherein the detector circuit is configured to switch the negative feedback node (Fbm) from the load ground node to an internal ground node, if the voltage (VFbm) exceeds a predetermined threshold voltage.

A packaged device includes a substrate, a die, a die flag, and a plurality of leads. The substrate has a lower surface and an upper surface opposite the lower surface. The die is arranged on the upper surface of the substrate. The die has a lower surface facing the upper surface of the substrate, and an upper surface opposite the lower surface. The die flag includes a cover portion which is arranged over the upper surface of the die. The cover portion has a lower surface and an upper surface opposite the lower surface. The lower surface of the cover portion faces the upper surface of the die. The plurality of leads is arranged around a periphery of the substrate. The plurality of leads includes a first lead connected to the die flag, and a second lead separated from the die flag. Each of the plurality of leads includes an outer portion which has a lower surface and an upper surface opposite the lower surface. The lower surfaces of the plurality of leads are coplanar with and separated from the lower surface of the substrate.