NXP USA

One example discloses a power regulator, including: a power output node configured to be coupled to a high-side of a load; a load ground node configured to be coupled to a low-side of the load; a negative feedback node (Fbm) configured to form a negative feedback path when coupled to the low-side of the load; a controller configured to regulate voltages at the power output node and the load ground node in response to a voltage on the negative feedback path; a current source configured to inject a current at the negative feedback node (Fbm); and a detector circuit configured to monitor a voltage (VFbm) at the negative feedback node (Fbm); wherein the detector circuit is configured to switch the negative feedback node (Fbm) from the load ground node to an internal ground node, if the voltage (VFbm) exceeds a predetermined threshold voltage.

A packaged device includes a substrate, a die, a die flag, and a plurality of leads. The substrate has a lower surface and an upper surface opposite the lower surface. The die is arranged on the upper surface of the substrate. The die has a lower surface facing the upper surface of the substrate, and an upper surface opposite the lower surface. The die flag includes a cover portion which is arranged over the upper surface of the die. The cover portion has a lower surface and an upper surface opposite the lower surface. The lower surface of the cover portion faces the upper surface of the die. The plurality of leads is arranged around a periphery of the substrate. The plurality of leads includes a first lead connected to the die flag, and a second lead separated from the die flag. Each of the plurality of leads includes an outer portion which has a lower surface and an upper surface opposite the lower surface. The lower surfaces of the plurality of leads are coplanar with and separated from the lower surface of the substrate.

An interposer structure and fabrication method are disclosed by providing a wafer substrate in which is formed FEOL transistors with gate oxides having a minimum specified thickness, forming a BEOL ILD stack with interconnect structures on the wafer substrate, selectively etching openings extending at least part way down through the BEOL ILD stack, filling the etch openings with at least deposited aluminum to form a plurality of aluminum via structures and aluminum crack stop structures extending from a top surface of the BEOL ILD stack at least part way down through the BEOL ILD stack, and partially recessing a bottom surface of the wafer substrate layer to expose at least the aluminum crack stop structures.

A distributed radar system includes a reference clock source, a first radar front end, and a second radar front end. The reference clock source is configured to generate a reference clock signal. The first radar front end is configured to generate a first radar chirp signal based on the reference clock signal received from the reference clock source. The second radar front end is configured to generate a second radar chirp signal by modulating a time period between consecutive chirps in the second radar chirp signal based on a second frequency signal that is generated by upconverting the reference clock signal received from the reference clock source.

A frame structure is described for aggregated data over a half-duplex serial data channel. In an example a serial link modem includes a transmit modem coupled to a serial channel and configured to send serial data through the serial channel, and an aggregator coupled to the transmit modem and configured to form a first frame type of serial data configured for data other than Universal Serial Bus (USB) data having an upstream packet and a downstream packet and a total length of less than a latency of two USB hubs, and a second frame type of serial data configured for USB data, wherein the aggregator forms the second frame type upon receiving USB data and wherein the transmit modem is configured to transmit the first frame type through the serial channel, and to transmit the second frame type through the serial channel upon completion of transmitting the first frame.

Embodiments of a repeater, an embedded Universal Serial Bus (eUSB) repeater, and a method of operating a repeater are disclosed. In an embodiment, a repeater includes a buffer configured to store data that is received during a time distance between an input start and a frame slot start, a counter configured to calculate a waiting time before starting frame transmission, and a transmitter configured to transmit predefined data at the frame slot start over a repeater channel and to transmit the data that is stored in the buffer over the repeater channel after the waiting time from the frame slot start.

Embodiments of a repeater (402), an embedded Universal Serial Bus (eUSB) repeater (402), and a method of operating a repeater (402) are disclosed. In an embodiment, a repeater (402) includes a timer (436) configured to generate a counter value that represents a time distance between a frame slot and a packet start and a modem (418) configured to transmit output data containing the counter value over a repeater channel (420).

An apparatus and method for mitigating received interference. Baseband signals received during a time interval by a first MIMO receiver and a second MIMO receiver are provided as in-phase and quadrature input streams of a complex valued input of a Discrete Fourier Transform (DFT) circuit that calculates a complex valued DFT dataset of the complex valued input. A complex valued interference mitigated frequency domain dataset is produced by determining an interference mask from a spectrogram of the complex valued DFT dataset and applying the interference mask to the spectrogram. An inverse DFT of the complex valued interference mitigated frequency domain dataset determines an interference mitigated complex valued time domain data stream that contains a first interference mitigated time series as its real valued data and a second interference mitigated time series as its imaginary valued data.

A receiver for a multi-antenna system and a method of generating channel estimations for the multi-antenna system are disclosed. In an embodiment, a receiver for a multi-antenna system comprises a detector configured to detect packets using signals received on a plurality of antennas, and a channel estimator configured to produce channel estimations based on the signals received on the plurality of antennas. The channel estimator is configured to estimate a relative channel with respect to first and second antenna using signals from first and second antennas to derive a relative channel estimation, estimate an antenna power for at least one of the first and second antennas using the signals from at least one of the first and second antennas, and compute channel estimations for the first and second antennas using the relative channel estimation and the antenna power for the at least one of the first and second antennas.

An integrated circuit assembly includes first and second circuit portions, an interposer vertically disposed between the first and second circuit portions, the interposer having a plated through hole with a metallic sidewall, and a metallic pillar that extends through the plated through hole without touching the metallic sidewall. The metallic pillar and the plated through hole together form a vertical coaxial structure constructed and arranged to convey RF (radio frequency) signals between the first and second circuit portions. Embodiments are directed to both the integrated circuit assembly and to a method of manufacturing the integrated circuit assembly.