IHP – Innovations for High Performance Microelectronics

The present invention relates to a method for fabricating an electronic or optoelectronic device (100). The method comprises the steps of:- providing a layer stack comprising along a stacking direction a wafer (105) and one or more dielectric mask layers;- structuring the one or more dielectric mask layers (107) by selectively etching at least one window into the one or more dielectric mask layers; and- selectively growing a nanostructure (102) of the electronic or optoelectronic device in the at least one window by means of epitaxy.

A reflection device for wireless communication comprises a two-dimensional array of reflective elements (109,119) and a control device (111,120) for controlling the multiple reflective elements such that the multiple reflective elements reflect the impinging electromagnetic waves in a phase-controlled fashion into a selectable reflection angle. The reflection device is configured to reflect and transform impinging electromagnetic waves having a first type of waveform, e.g. plane waves, such that the reflected electromagnetic waves have a second type of waveform, e.g. orbital angular momentum (OAM) waves, and vice versa. Instead of using OAM waves as second type of electromagnetic waves, LOS-MIMO can be used as well. Furthermore, a transformation between LOS-MIMO waves to OAM-waves and vice versa, is equally possible.

For generation of a physical-layer secret key for use in wireless communication, a first transceiver and a second transceiver, both with beamforming capability, in a sequence of repetitions covering a plurality of beam pairs from a beamforming codebook defining a set of beam pairs, select a transmit beam angle and a receive beam angle in respective random order unknown to the respective other transceiver, for probe signal exchange and determining respective versions of channel state information. The channel state information versions are used to determine, after quantization and reconciliation, sub-keys associated with the respective beam pairs, which are combined to obtain a composite physical-layer secret key.

A calibration method for operating a CW short-range radar system in obtaining calibrated intermediate frequency in-phase and quadrature outputs comprises measuring at least one reflective static calibration target at a plurality of at least four different target ranges and processing the received CW radar measurement signal by performing a quadrature downconversion of the received CW radar beam intensity and phase to obtain measured intermediate frequency in-phase outputs and intermediate frequency quadrature outputs. These are used to solve a system of equations for calibration parameter values including an amplitude mismatch a phase mismatch between the quadrature signals, and individual DC offsets of the quadrature signals.

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

Es wird eine SDTMR-Speicherzelle (100) zum Speichern digitaler Daten mit mindestens drei bistabilen Speicherelementen (FF1,FF2,FF3) vorgeschlagen, die in einer Normalbetriebsart ein digitales Eingangssignal und ein Taktsignal empfangen. Jedes bistabile Speicherelement gibt ein Ausgangssignal an einen Voter (101) ab, der an einem ersten Ausgang der Speicherzelle ein Ausgangssignal gemäß der Majorität der digitalen Eingangssignale erzeugt. Die Speicherzelle hat auf Basis der Triple-Modular-Redundancy (TMR) fehlerkorrigierende Eigenschaften. Die Speicherzelle ist wahlweise in eine Scanbetriebsart umschaltbar, in welcher die bistabilen Speicherelemente zu einem Schieberegister verbunden sind. In der Scanbetriebsart ist es möglich, interne Einzelbitfehler zu detektieren, trotz der fehlerkorrigierenden Eigenschaften, welche die Speicherzelle im Normalbetrieb hat. Weiterhin wird ein Verfahren zur Erzeugung von Testmustern vorgeschlagen, um die SDTMR-Zellen auf interne Bitfehler zu prüfen. Dabei greift das Verfahren sowohl auf die Netzliste einer Schaltung, welche SDTMR-Zellen enthält, als auch auf die Netzliste der verwendeten SDTMR-Zelle zu. Das Testmuster gestattet es, die Schaltung auf interne Bitfehler zu prüfen.

Zusammenfassung wird geladen …

An apparatus and a method for recovering clock and data from a multilevel pulse amplitude modulated signal received as input signal (Din) is suggested. The apparatus (500) comprises a phase detector (101), a low-pass filter (102), a voltage-controlled oscillator (103), and a feedback loop forming a CDR loop (107). The voltage-controlled oscillator outputs a clock signal (CKout) that is provided to the phase detector (101). The phase detector receives an MSB signal from a sampler. The apparatus also comprises an interleave circuit (501) configured to receive the input signal (Din) and to generate two output signals (HR1 ,HR2) having a smaller symbol rate than the input signal. The apparatus further comprises a logical gate (508) configured to receive the output signals from the interleave circuit (501) and to generate an enable signal for the phase detector (101) indicating symmetrical transitions in the input signal. Lastly, the apparatus comprises a converter (502) converting the output signals (HR1,HR2) from the interleave circuit (501) into an MSB and an LSB bit stream.