Nvidia Patente

Apparatuses, systems, and techniques to use one or more neural networks to generate one or more responses to the one or more user queries. In at least one embodiment, a processor comprises processing circuitry to use one or more neural networks to generate computer program code to obtain performance information of one or more programs performed by one or more graphics processing units (GPUs) based, at least in part, on one or more user queries indicating the one or more programs and perform the computer program code to generate one or more responses to the one or more user queries.

Apparatuses, systems, and techniques to identify one or more processing units to generate one or more data structures to use a memory accelerator. In at least one embodiment, a processor comprises processing circuitry to identify one or more processing units to generate one or more data structures to use a memory accelerator based, at least in part, on computer program code indicating one or more data transfers and compile the computer program code to cause the one or more processing units to generate the one or more data structures to use the memory accelerator.

Apparatuses, systems, and techniques to calculate efficiency metrics associated with performing operations of a software program a first type of processor compared to a second type of processor. In at least one embodiment efficiency metrics associated with performing operations are used to determine whether the operation is to be executed by the first processor type or by the second processor type.

A server rack includes an optical patch panel and a plurality of processing units. The optical patch panel includes a plurality of L1 connections, a plurality of L2 connections, and a removable connectivity cartridge optically connecting the plurality of L1 connections and the plurality of L2 connections. The plurality of processing units is connected to an L2 domain of a datacenter through the removable connectivity cartridge of the optical patch panel.

Apparatuses, systems, and techniques to compile computer program code to cause one or more memory accelerators to be used to access a plurality of memory locations. In at least one embodiment, computer program code is compiled to cause one or more memory accelerators to be used to access a plurality of memory locations based on, for example, an indication of a layout of the plurality of memory locations in the computer program code.

Processors, systems, and techniques to cause a compiler to partition a tile of a tile program into a plurality of sub-tiles and perform tile program operations on the sub-tiles in a determined order. In at least one embodiment a compiler is to partition a tile of a tile program into a plurality of sub-tiles, wherein the compiler determines a size of the sub-tiles based, at least in part, on one or more accelerator hardware characteristics. The compiler is further to generate a plurality of instruction groups to be performed on corresponding sub-tiles of the plurality of sub-tiles, wherein the instruction groups are based, at least in part, on a tile operation to be performed on the tile of the tile program, determine an order to perform individual instruction groups of the plurality of instruction groups, and generate code to cause individual instruction groups to be performed in the determined order.

A waveguide includes an inner rib comprising a core of the waveguide. The waveguide further includes first and second outer ribs having at least one structural feature different from the inner rib.

Processors, systems, and techniques to generate schedules of operations of tile-based programs in accordance with constants on usage of functional units ofan accelerator. In at least one embodiment a compiler is to generate a dependency graph indicative of operations of a tile program and determine functional units of an accelerator that would be used to perform operations in a first order indicated by the dependency graph. The compiler is further to determine a second order in which to perform the operations of the tile program based, at least in part, on constraints on usage of the determined functional units, and generate code to perform the tile program based, at least in part, on the second order.

According to an aspect of the present disclosure, a power management module configured for powering a server tray is provided. In an example embodiment, the power management module includes a housing; a busbar connector extending from a first side of the housing; power management circuitry; and a tray connector accessible via a second side of the housing. The power management circuitry includes at least one fuse component, and is in electrical communication with the busbar connector. The tray connector is configured to provide electrical power to the server tray.

According to an aspect of the present disclosure, a tray is provided that includes a plurality of groups of processing units. Each group of processing units includes one or more processing units in communication with one another. In certain embodiments, communication between pairs of groups of processing units is enabled by an on-tray communication bridge. Each of the one or more processing units are one of a CPU, GPU, DPU, QPU, PPU and/or the like.

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Inter-process communication methods that divide a total payload of a first memory command among a plurality of packets and that encode a last-transmitted packet of the plurality of packets to include a metadata code in the total payload. The memory command may be communicated between processes executing a collective operation. Payloads of the packets are written to memory in a sequential address order, such that the metadata code is written to a particular address, and the second process generates an acknowledgment of the first memory command to the first process on condition that reading the particular address returns the metadata code.

Apparatuses, systems, and techniques to use neural networks to predict an amount of computing resources to allocate to perform software programs based on characteristics of the software programs and power to be used to perform software programs, to generate updates to equations to predict a first amount of computing resources to perform software programs from an amount of power consumed by a second amount of computing resources to perform said software program, and/or to predict a power efficiency of processors based on software ptograms to be performed by said processors.

Apparatuses, systems, and techniques to prevent one or more scheduled instructions identified by one or more users from being performed. In at least one embodiment, one or more scheduled instructions identified by one or more users are prevented from being performed based on, for example, an application programming interface (API).

Apparatuses, systems, and techniques to perform beamforming in a wireless network. In at least one embodiment, a processor identifies two or more directions to transmit two or more wireless signals based, at least in part, on one or more matrix operands each comprising two or more beamforming matrices and transmit said wireless signals in said identified directions.

A device includes a transmitter coupled to a communication network, a first controller coupled to the transmitter via a control channel, and control logic coupled to the first controller and the transmitter, the control logic to: determine whether the first controller is synchronized with a respective controller of a second device; cause the transmitter to transmit a first number of communications based on a first encryption key in response to a determination that the first controller is synchronized with the respective controller; determine whether the first number of communications satisfies a first threshold condition based on a first encryption interval corresponding to the first encryption key; and cause the transmitter to transmit a second number of communications based on a second encryption key in response to a determination that the first number of communications satisfies the first threshold condition.

Apparatuses, systems, and techniques translate program instructions that use references to access objects stored in memory to program instructions that use register identifiers to access objects stored in registers. In at least one embodiment, a compiler translates one or more references to one or more corresponding register identifiers.

Apparatuses, systems, and methods to perform thread memory addressing. In at least one embodiment, a processor comprising one or more circuits to perform an application programming interface (API) to generate one or more addresses for one or more instructions corresponding to a same software kernel.

Apparatuses, systems, and techniques to perform a digital simulation of a wireless network. In at least one embodiment, a processor generates a virtual network simulation and combine user equipment of said virtual network simulation into virtual cells in order to cause at least one of two or more mobile device emulation programs to be selected based, at least in part, on two or more distinct physical resource block parameters corresponding to said two or more mobile devices.

Apparatuses, systems, and techniques to identify a clock frequency at which one or more processors are to operate. In at least one embodiment, a processor performs an application programming interface (API) to cause one or more one or more activity levels of one or more processors to be measured at one or more indicated intervals.

Apparatuses, systems, and techniques to perform operations in a processor asynchronously. In at least one embodiment, a processor performs perform at least one tensor instruction concurrently with one or more other instructions based, at least in part, on one or more indicators of the tensor instruction being asynchronous.

Systems and methods for atomic memory operations in a remote direct memory access network are disclosed. A system includes a network interface card (NIC) comprising a first memory and one or more processors coupled to the first memory. The one or more processors are to receive an atomic memory operation (AMO) remote procedure call (RPC) comprising a memory address and an AMO type. The one or more processors are further to retrieve a value corresponding to the memory address of the AMO RPC from a second memory. The one or more processors are further to perform an AMO corresponding to the AMO type on the value from the second memory to obtain a modified value. The one or more processors are further to store the modified value in the first memory.

Apparatuses, systems, and techniques to translate instructions that use operand stack structures to instructions that use registers and/or memory for operands. In at least one embodiment, one or more instruction operand stack structures are duplicated if one or more branch instructions use one or more instruction operands stored in the one or more stack structures.

Apparatuses, systems, and methods to store non-graphics kernels with graphics kernels. In at least one embodiment, performance of an application programming interface ("API") causes non-graphics kernels to be stored sequentially with graphics kernels to be performed by one or more processors.

Apparatuses, systems, and techniques to simulate communicated between wireless devices and base stations. In at least one embodiment, communication between wireless devices and base stations are simulated based on a grouping of wireless devices according to shared communication frequency bands.

Apparatuses, systems, methods, and/or techniques to identify anomalies in a computer network topology. In at least one embodiment, a first portion of a computer network is used to train a model and the train model is applied to a second portion of the network to predict link connections in the second portion. In at least one embodiment, such predictions are used to identify topology amomalies.

Apparatuses, systems, and techniques to perform third party management of operational thread memory requests within one or more processors by use of a server to manage said memory and memory requests to perform dynamic memory allocation during runtime without overwrite risk, according to at least one embodiment. In at least one embodiment, processor scomprising one or more circuits to cause one or more threads to use one or more virtual storage location addresses to access one or more physical storage locations based, at least in part, on information indicating whether the one or more physical storage locations are allocated to the one or more threads.

Apparatuses, systems, and methods to perform thread memory addressing. In at least one embodiment, a processor, comprising: one or more circuits to perform an application programming interface (API) to cause one or more instructions to be performed based, at least in part, one or more API parameters indicating a size of one or more operands to be used by the one or more instructions.

Apparatuses, systems, and methods to modify compressed videos. In at least one embodiment, a processor includes circuitry to perform one or more instructions to cause information to be stored and to store an indication of one or more decompression algorithms to decompress the information.

Apparatuses, systems, and techniques to use one or more neural networks to cause one or more error detection and correction (EDC) algorithms to be performed for one or more radio access network (RAN) signals. In at least one embodiment, one or more EDC algorithms are to be performed on said one or more RAN signals based, at least in part, on one or more quality indicators of said one or more RAN signals.

Apparatuses, systems, and techniques to perform substantiation of task pipelines for sequential tasks performed by simultaneous, sequential kernels. In at least one emodiment, processors comprising one or more circuits to cause a compiler to indicate one or more portions of one or more software programs to be performed by one or more processors concurrently.

Apparatuses, systems, and techniques to perform decompression on compressed data. In at least one embodiment, a processor perform an application programming interface to cause information to be decompressed and stored in one or more storage locations indicated by a user.

A deformation assembly, in at least one aspect, may support a cold plate assembly or may be part of the cold plate assembly which includes a cold plate. The deformation assembly may allow a controlled deformation to the cold plate. The controlled deformation may deform the cold plate to a predetermined curvature of a computing component.

Apparatuses, systems, and techniques to determine a channel delay time. In at least one embodiment, the channel delay time is used to determine a buffer size and/or a watchdog timer period. In at least one embodiment, if a disruption occurs, the system may route data traffic to a different communication channel to bypass a disruption in a communication channel.

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