Nvidia

Inter-process communication methods that divide a total payload of a first memory command among a plurality of packets and that encode a last-transmitted packet of the plurality of packets to include a metadata code in the total payload. The memory command may be communicated between processes executing a collective operation. Payloads of the packets are written to memory in a sequential address order, such that the metadata code is written to a particular address, and the second process generates an acknowledgment of the first memory command to the first process on condition that reading the particular address returns the metadata code.

Apparatuses, systems, and techniques to prevent one or more scheduled instructions identified by one or more users from being performed. In at least one embodiment, one or more scheduled instructions identified by one or more users are prevented from being performed based on, for example, an application programming interface (API).

Apparatuses, systems, and techniques to use neural networks to predict an amount of computing resources to allocate to perform software programs based on characteristics of the software programs and power to be used to perform software programs, to generate updates to equations to predict a first amount of computing resources to perform software programs from an amount of power consumed by a second amount of computing resources to perform said software program, and/or to predict a power efficiency of processors based on software ptograms to be performed by said processors.

Apparatuses, systems, and techniques to perform beamforming in a wireless network. In at least one embodiment, a processor identifies two or more directions to transmit two or more wireless signals based, at least in part, on one or more matrix operands each comprising two or more beamforming matrices and transmit said wireless signals in said identified directions.

A device includes a transmitter coupled to a communication network, a first controller coupled to the transmitter via a control channel, and control logic coupled to the first controller and the transmitter, the control logic to: determine whether the first controller is synchronized with a respective controller of a second device; cause the transmitter to transmit a first number of communications based on a first encryption key in response to a determination that the first controller is synchronized with the respective controller; determine whether the first number of communications satisfies a first threshold condition based on a first encryption interval corresponding to the first encryption key; and cause the transmitter to transmit a second number of communications based on a second encryption key in response to a determination that the first number of communications satisfies the first threshold condition.

Apparatuses, systems, and methods to perform thread memory addressing. In at least one embodiment, a processor comprising one or more circuits to perform an application programming interface (API) to generate one or more addresses for one or more instructions corresponding to a same software kernel.

Apparatuses, systems, and techniques translate program instructions that use references to access objects stored in memory to program instructions that use register identifiers to access objects stored in registers. In at least one embodiment, a compiler translates one or more references to one or more corresponding register identifiers.

Apparatuses, systems, and techniques to perform a digital simulation of a wireless network. In at least one embodiment, a processor generates a virtual network simulation and combine user equipment of said virtual network simulation into virtual cells in order to cause at least one of two or more mobile device emulation programs to be selected based, at least in part, on two or more distinct physical resource block parameters corresponding to said two or more mobile devices.

Systems and methods for atomic memory operations in a remote direct memory access network are disclosed. A system includes a network interface card (NIC) comprising a first memory and one or more processors coupled to the first memory. The one or more processors are to receive an atomic memory operation (AMO) remote procedure call (RPC) comprising a memory address and an AMO type. The one or more processors are further to retrieve a value corresponding to the memory address of the AMO RPC from a second memory. The one or more processors are further to perform an AMO corresponding to the AMO type on the value from the second memory to obtain a modified value. The one or more processors are further to store the modified value in the first memory.

Apparatuses, systems, and techniques to identify a clock frequency at which one or more processors are to operate. In at least one embodiment, a processor performs an application programming interface (API) to cause one or more one or more activity levels of one or more processors to be measured at one or more indicated intervals.