Nvidia

Apparatuses, systems, and techniques to use one or more neural networks to generate one or more responses to the one or more user queries. In at least one embodiment, a processor comprises processing circuitry to use one or more neural networks to generate computer program code to obtain performance information of one or more programs performed by one or more graphics processing units (GPUs) based, at least in part, on one or more user queries indicating the one or more programs and perform the computer program code to generate one or more responses to the one or more user queries.

Processors, systems, and techniques to cause a compiler to partition a tile of a tile program into a plurality of sub-tiles and perform tile program operations on the sub-tiles in a determined order. In at least one embodiment a compiler is to partition a tile of a tile program into a plurality of sub-tiles, wherein the compiler determines a size of the sub-tiles based, at least in part, on one or more accelerator hardware characteristics. The compiler is further to generate a plurality of instruction groups to be performed on corresponding sub-tiles of the plurality of sub-tiles, wherein the instruction groups are based, at least in part, on a tile operation to be performed on the tile of the tile program, determine an order to perform individual instruction groups of the plurality of instruction groups, and generate code to cause individual instruction groups to be performed in the determined order.

According to an aspect of the present disclosure, a tray is provided that includes a plurality of groups of processing units. Each group of processing units includes one or more processing units in communication with one another. In certain embodiments, communication between pairs of groups of processing units is enabled by an on-tray communication bridge. Each of the one or more processing units are one of a CPU, GPU, DPU, QPU, PPU and/or the like.

According to an aspect of the present disclosure, a power management module configured for powering a server tray is provided. In an example embodiment, the power management module includes a housing; a busbar connector extending from a first side of the housing; power management circuitry; and a tray connector accessible via a second side of the housing. The power management circuitry includes at least one fuse component, and is in electrical communication with the busbar connector. The tray connector is configured to provide electrical power to the server tray.

Processors, systems, and techniques to generate schedules of operations of tile-based programs in accordance with constants on usage of functional units ofan accelerator. In at least one embodiment a compiler is to generate a dependency graph indicative of operations of a tile program and determine functional units of an accelerator that would be used to perform operations in a first order indicated by the dependency graph. The compiler is further to determine a second order in which to perform the operations of the tile program based, at least in part, on constraints on usage of the determined functional units, and generate code to perform the tile program based, at least in part, on the second order.

A waveguide includes an inner rib comprising a core of the waveguide. The waveguide further includes first and second outer ribs having at least one structural feature different from the inner rib.

A server rack includes an optical patch panel and a plurality of processing units. The optical patch panel includes a plurality of L1 connections, a plurality of L2 connections, and a removable connectivity cartridge optically connecting the plurality of L1 connections and the plurality of L2 connections. The plurality of processing units is connected to an L2 domain of a datacenter through the removable connectivity cartridge of the optical patch panel.

Apparatuses, systems, and techniques to identify one or more processing units to generate one or more data structures to use a memory accelerator. In at least one embodiment, a processor comprises processing circuitry to identify one or more processing units to generate one or more data structures to use a memory accelerator based, at least in part, on computer program code indicating one or more data transfers and compile the computer program code to cause the one or more processing units to generate the one or more data structures to use the memory accelerator.

Apparatuses, systems, and techniques to calculate efficiency metrics associated with performing operations of a software program a first type of processor compared to a second type of processor. In at least one embodiment efficiency metrics associated with performing operations are used to determine whether the operation is to be executed by the first processor type or by the second processor type.

Apparatuses, systems, and techniques to compile computer program code to cause one or more memory accelerators to be used to access a plurality of memory locations. In at least one embodiment, computer program code is compiled to cause one or more memory accelerators to be used to access a plurality of memory locations based on, for example, an indication of a layout of the plurality of memory locations in the computer program code.