Samsung Display Patente

A display device includes: a circuit layer; an element layer on the circuit layer and including a plurality of light emitting elements; an input sensing layer on the element layer, and including a plurality of sensing electrodes; and a sensor controller configured to control driving of the input sensing layer, wherein the circuit layer includes: a plurality of pixel circuits connected to the plurality of light emitting elements, respectively, and repeatedly arranged in a first direction; a plurality of wirings connected to the plurality of pixel circuits and extending in a second direction crossing the first direction; and a loop wiring connected to the sensor controller and having a loop form, wherein the loop wiring and at least one of the plurality of wirings are on a same layer.

A digitizer includes a base layer including a folding portion in which through-holes are defined and a non-folding portion adjacent to the folding portion in a first direction, and sensing coils disposed on the base layer. Each of the through-holes is defined as a first hole extending in a second direction intersecting the first direction, a second hole defined at a first end of the first hole, and a third hole defined at a second end of the first hole opposite to the first end. A first width of the first hole in the first direction is smaller than a second width of each of the second hole and the third hole in the first direction.

A display device includes a data driver to provide data voltages, a scan driver to sequentially provide scan signals, and a controller to control the data driver and the scan driver, wherein a scan driver stage includes an input circuit to transfer an input signal to a control node in response to a clock signal, a node-controlling circuit to provide a high gate voltage to an inverted control node when a voltage of the control node has a low level, and to provide a low gate voltage to the inverted control node when voltages of the control node and the clock signal have the high level, and an output circuit to output the high gate voltage as the scan signal in response to a voltage of the inverted control node, and to output the low gate voltage as the scan signal in response to the voltage of the control node.

A pixel includes a first sub-pixel including a first light-emitting element connected between a high voltage power supply line to transmit a high power supply voltage and a first low voltage power supply line to transmit a first low power supply voltage lower than the high power supply voltage, and a second sub-pixel including a second light-emitting element connected between the high voltage power supply line and a second low voltage power supply line to transmit a second low power supply voltage lower than the high power supply voltage. The first low power supply voltage is higher than the second low power supply voltage.

A display panel includes a base layer, a transistor disposed on the base layer, a common electrode disposed on the transistor, a conductive barrier wall that is disposed on the common electrode and that has a barrier wall opening, a barrier wall insulating layer disposed on the conductive barrier wall, and a light emitting element that is disposed on the barrier wall insulating layer and that includes a first electrode electrically connected to the transistor, an emission pattern disposed on the first electrode, and a second electrode disposed on the emission pattern and electrically connected with the conductive barrier wall.

A pixel (PXL1; PXL1') includes first to seventh transistors (TR7). Gate electrodes of the first to seventh transistors (TR7) are connected to a first node (N1), a third scan line (SL3i), a first scan line (SL1i), a second scan line (SL2i), a first light emission control line (EL1i), a second emission control line, and a third scan line (SL3i), respectively. The first to seventh transistors (TR7) are connected between a second node (N2) and a third node (N3), a data line (DLj) and the first node (N1), a reference power node (VREFN) and the first node (N1), the initialization power node (VINTN) and a fourth node (N4), a first driving power node (ELVDDN) and the third node (N3), the second node (N2) and the fourth node (N4), and the second node (N2) and the third node (N3), respectively. A light emitting element (LD) is connected to the fourth node (N4). The seventh transistor (TR7) is turned on in response to a scan signal (GWi) applied to the third scan line (SL3i) connecting the second node (N2) and the third node (N3).

A light emitting display device according to an embodiment includes a display area where a plurality of repeating unit pixels are iteratively provided, the repeating unit pixel includes a plurality of minimum unit pixels, the minimum unit pixel includes at least one red subpixel, at least one green subpixel, and at least one blue subpixel, the green subpixel, the red subpixel, and the blue subpixel correspond to a first opening provided in a pixel defining layer and a second opening provided above the first opening while corresponding to the first opening, at least one of the first opening and the second opening has an elliptical shape in planar shape, and the repeating unit pixel is formed of minimum unit pixels provided in a 2x2 array.

A stage circuit includes a first input terminal configured to receive a clock signal, a second input terminal configured to receive a driving signal, an output terminal configured to output a carry signal, an input circuit configured to transmit the driving signal to a first node in response to the clock signal, a voltage control circuit that controls voltages of a first control node and a second control node in response to the driving signal transmitted to the first node, and a carry driver circuit including a boosting capacitor connected between the first control node and the output terminal, and a buffer capacitor configured to maintain the voltage of the output terminal.

A light emitting display device may include a substrate including a normal display area divided into an edge area and a central area, an anode located on the substrate, a pixel defining layer including a first opening configured to expose at least a portion of the anode, an emission layer located within the first opening of the pixel defining layer, a cathode configured to cover the pixel defining layer and the emission layer, an encapsulation layer configured to cover the cathode and including an organic encapsulation layer, and a second opening located on the encapsulation layer, and corresponding to the first opening of the pixel defining layer, where the second opening is divided into a central second opening located in the central area and an edge second opening located in the edge area, and where the edge second opening is smaller than the central second opening.

A window member comprises a cover window, an optical member disposed on the cover window, and a functional member disposed on the optical member. The optical member comprises a first refractive layer disposed on the cover window, and at least two groups disposed on the first refractive layer. Each of the at least two groups comprises a second refractive layer and a third refractive layer. The second refractive layer and the third refractive layer have different refractive indices from each other. The first refractive layer has a first refractive index between a second refractive index of the second refractive layer and a third refractive index of the third refractive layer. The first refractive layer contains at least silicon.

A method of manufacturing a display device includes forming a plurality of display cells on a first surface of a mother substrate which includes the first surface and a second surface facing the first surface, forming a plurality of first sketch lines extending from the first surface toward the second surface and located along edges of the plurality of display cells, based on irradiating a laser beam onto at least one of the first surface or the second surface, slimming the mother substrate to form a slimmed mother substrate based on spraying an etchant onto the second surface, and separating the plurality of display cells from the slimmed mother substrate based on dividing the mother substrate based on positioning a stage that includes first step portions in relation to the slimmed mother substrate such that each first step portion is adjacent to a separate first sketch line.

An electronic device includes: a display layer configured to display an image; a sensor layer on the display layer; a first magnetic field induction layer under the display layer; and a second magnetic field induction layer under the display layer, and spaced from the first magnetic field induction layer. The sensor layer includes: a plurality of first electrodes along a first direction; a plurality of second electrodes along a second direction crossing the first direction; a plurality of third electrodes along the first direction; and a loop trace line electrically connected with all of the plurality of third electrodes. The first magnetic field induction layer and the second magnetic field induction layer are spaced from each other in the second direction.

A display panel includes a substrate. A display layer is arranged over the substrate and including a plurality of display elements emitting light of different colors from each other. An encapsulation member is coupled to the substrate and shields the display layer. A light-blocking layer is arranged over the encapsulation member and including a plurality of opening portions respectively corresponding to the plurality of display elements. A plurality of color filters is arranged in the light-blocking layer to respectively correspond to the plurality of display elements. A refractive layer is arranged over the plurality of color filters and has a refractive index in a range of about 1 to about 1.5.

A display device including a substrate, an insulating layer above the substrate, a via electrode within a via hole of the insulating layer, a planarization layer defining a through hole overlapping the via electrode and a portion of the insulating layer around the via electrode, a connection electrode above the planarization layer in the through hole, a reflective electrode above the connection electrode in the through hole, an optical auxiliary layer above the reflective electrode, a first electrode above the optical auxiliary layer, and having an edge facing an edge of the connection electrode and contacting the edge of the connection electrode without a step, a light-emitting stack above the first electrode, and a second electrode above the light-emitting stack.

A release film includes a first sub-release film including a first body portion attached to a display module and at least one first grip portion that protrudes from the first body portion and a second sub-release film disposed under the first sub-release film and including a second body portion attached to the first body portion and at least one second grip portion that protrudes from the second body portion. Here, the first grip portion overlaps with the second grip portion.

Discloses are a quantum dot device including an anode disposed on the substrate and including a reflective layer, a hole auxiliary layer disposed on the anode and including a hole injection layer, a hole transport layer, or a combination thereof, a quantum dot layer disposed on the hole auxiliary layer and including quantum dots, an electron auxiliary layer disposed on the quantum dot layer, and a cathode disposed on the electron auxiliary layer and the cathode being a light-transmitting electrode capable of transmitting at least a portion of light emitted from the quantum dot layer, wherein the quantum dot layer is configured to emit light of a first wavelength spectrum that is one of a blue wavelength spectrum, a green wavelength spectrum, and a red wavelength spectrum, the hole auxiliary layer has a thickness in which a resonant wavelength of the quantum dot device falls within the first wavelength spectrum, an peak emission wavelength of the quantum dot layer and an peak emission wavelength of the light passing through the cathode belong to the first wavelength spectrum in common, and a full width at half maximum (FWHM) of the emission spectrum of light passing through the cathode is narrower than that of the emission spectrum of the quantum dot layer, and a quantum dot display device including the same.

A pixel includes: a driving transistor including: a source region electrically connected to a driving voltage line, which receives a driving voltage and disposed in one side of a semiconductor substrate, a drain region disposed in an opposite side of the semiconductor substrate, a channel region disposed in a portion of the semiconductor substrate between the source region and the drain region and having an asymmetrical shape with respect to a center of the channel region, an insulating layer disposed on the channel region, and a gate electrode disposed on the insulating layer and overlapping the channel region in a plan view, wherein the driving transistor is configured to generate a driving current, and a light-emitting element, which generates light based on the driving current and including an anode electrode and a cathode electrode.

A display device (10) according to the present disclosure includes a substrate (110), a transistor (TR) on a surface of the substrate (110), an under-anode insulating layer (129) disposed on the transistor (TR) and including first and second portions (131a, 131b) having different thicknesses (t) from each other and a third portion connecting the first and second portions (131a, 131b), a pixel electrode (131) on the first portion (131a), the second portion (131b), and the third portion, a pixel defining layer (135) on the pixel electrode (131) and the under-anode insulating layer (129), a light-emitting layer (132) on the pixel electrode (131), and a common electrode (133) on the light-emitting layer (132) and the pixel defining layer (135). The under-anode insulating layer (129) includes a first under-anode insulating layer (1291) including a first hole (H1) in the first portion (131a) , and a second under-anode insulating layer (1292) defining or including at least a portion within the first hole (H1) and corresponding to or contacting the first portion (131a). The first under-anode insulating layer (1291) includes an inorganic material, and the second under-anode insulating layer (1292) includes an organic material.

A light-emitting device including a condensed cyclic compound represented by Formula 1, an electronic apparatus including the light-emitting device, and the condensed cyclic compound represented by Formula 1 are provided. <img class="EMIRef" id="9c5baeaa-700b-41d6-af0a-8c21d47a3a89-ia01" /> A detailed description of Formula 1 is provided.

Provided is a display device (DD) including a base layer (BS) including a non-display region (DA) (NDA), and a display region (DA) that includes a first light-emitting region (PXA-B), a second light-emitting region (PXA-G), and a non-light-emitting region (NPXA), a display element layer (EDL) above the base layer (BS) and including a light-emitting element (ED), and an optical layer (PP) above the display element layer (EDL) and including a first color filter (CF-B) overlapping the first light-emitting region (PXA-B), a scattering pattern (SP1, SP2) overlapping the second light-emitting region (PXA-G) and including scattering particles, a second color filter (CF-G) overlapping the second light-emitting region (PXA-G) above the scattering pattern (SP1, SP2), and a light-blocking layer (BM) overlapping the non-light-emitting region (NPXA) between the first color filter (CF-B) and the second color filter (CF-G), and partially covering an upper surface (U-CB) of the first color filter (CF-B).

Each of a plurality of stages of a driving circuit includes an input circuit (131) configured to transmit a start signal (STV) to a first node (A), a first output circuit (135a) connected to a first terminal (V1) to which a first voltage (VGH) is input and a second terminal (V2) to which a second voltage is input (VGL), the first output circuit being configured to output an output signal (GOUT) to a signal line, a second output circuit (137a) connected to the first terminal and a third terminal (V3) to which a third voltage (VGL2) is input, the second output circuit being configured to output a carry signal (COUT) to a next stage, and a control circuit (133a) configured to control voltages of nodes (QB, Q) to which the first output circuit and the second output circuit are connected according to a voltage of the first node.

Provided is a display apparatus including a substrate, a planarization layer above the substrate, a first pixel electrode above the planarization layer, an emission layer above the first pixel electrode, an opposite electrode above the emission layer, and a pixel-defining layer between the emission layer and the opposite electrode, and defining a first pixel opening overlapping the first pixel electrode.

A display device includes pixel circuit units arranged in a first direction, a repair pixel circuit unit, conductive lines connected to the pixel circuit units, and a repair line crossing the pixel circuit units and the repair pixel circuit unit, the pixel circuit units and the repair pixel circuit unit including a first capacitor between first and second nodes, a first transistor including a gate connected to the first node, a first terminal, and a second terminal connected to the second node, and a second capacitor connected between the second node and a first power supply voltage, and wherein a first ratio of a capacitance of the first capacitor to a capacitance of the second capacitor of the repair pixel circuit unit is less than a second ratio of a capacitance of the first capacitor to a capacitance of the second capacitor of the pixel circuit units.

A deposition mask may include a mask substrate having a cell opening, a membrane on (e.g., disposed on) the mask substrate and having pixel openings communicating with the cell opening, and a mask alignment key on (e.g., disposed on) the mask substrate. The mask alignment key may include a pattern region and a peripheral region around (e.g., surrounding) the pattern region, and the pattern region may include a surface modified region having a greater surface roughness than the peripheral region.

A display device may include a hole, a display element, a switching element, a groove, a planarization layer, and a cover layer. The switching element may be electrically connected to the display element. The encapsulation layer may cover the display element. The groove may be located between the hole and the display element. A portion of the planarization layer may be located between a first edge of the planarization layer and a second edge of the planarization and may be located in the groove. The first edge of the planarization layer may be located closer to the display element than the second edge of the planarization layer. The cover layer may at least partially cover the first edge of the planarization layer.

A gate driver for a display device is provided including a first stage having an output terminal connected to a plurality of pixels of the display device. The first stage comprises a second transistor including a first electrode configured to receive a first voltage. A third capacitor includes a first electrode connected to the second electrode of the second transistor, and a second electrode. An eleventh transistor includes and a gate electrode configured to receive a second voltage lower than the first voltage. A second capacitor includes a first electrode connected to the second electrode of the eleventh transistor, and a second electrode. A sixth transistor includes a gate electrode connected to a second clock signal line. A ninth transistor includes a first electrode configured to receive the first voltage. A tenth transistor includes a second electrode configured to receive the second voltage. A sixteenth transistor includes a first electrode connected to the second electrode of the third capacitor, a second electrode connected to the gate electrode of the tenth transistor, and a gate electrode connected to the second electrode of the third capacitor.

A display device is disclosed that includes a substrate, a thin film transistor on the substrate, an insulating layer on the thin film transistor; and a light-emitting element. The light-emitting element is positioned on the insulating layer and includes a pixel electrode electrically connected to the thin film transistor, a common electrode facing the pixel electrode, and an interlayer between the pixel electrode and the common electrode. A pixel definition film is positioned on the insulating layer and covers an edge of the pixel electrode to define a light-emitting area of the light-emitting element. The common electrode includes a first common electrode on the light-emitting area, a second common electrode spaced apart from the first common electrode and surrounding the light-emitting area and positioned on the pixel definition film, and a bridge electrode connecting the first common electrode to the second common electrode.

A display panel includes a light-emitting diode. The light-emitting diode includes a first driving electrode, a light-emitting layer and a second driving electrode. The light-emitting layer is disposed on the first driving electrode. The second driving electrode is disposed on the light-emitting layer. The second driving electrode includes a first conductive layer and a second conductive layer. The first conductive layer has a first thickness. The second conductive layer contacts the first conductive layer. The second conductive layer includes silver. The second conductive layer is disposed on the first conductive layer. The second conductive layer has a second thickness greater than or equal to 7 times of the first thickness and smaller than or equal to 15 times of the first thickness.

An electronic device including a display device, a first body and a second body in a first direction under the display device, a bracket between the first body and the second body, a first rotator and a second rotator between the first body and the bracket and between the second body and the bracket, respectively, a first rotation link and a second rotation link facing the first rotator and the second rotator, respectively, in a second direction crossing the first direction, and a plurality of protruding pins protruding from the first rotation link and the second rotation link toward the first rotator and the second rotator, respectively, and in guide grooves defined on surfaces of the first rotator and the second rotator facing the first rotation link and the second rotation link. The guide grooves include first guide groove, and a second guide groove extending from the first guide groove.

A light emitting element including a first electrode, a hole transport region, an emission layer, an electron transport region, and a second electrode. The hole transport region includes a monoamine compound represented by Formula 1 below. Accordingly, the light emitting element of an aspect may exhibit high luminous efficiency and long life. <img class="EMIRef" id="538b72df-936a-4411-b484-c4bcf89c5a24-ia01" />

A display device includes a bank structure in which an anode contact hole is defined in an emission area, the bank structure having a side surface defining the anode contact hole and an overhang structure which is in the non-emission area, a first insulating layer on the bank structure and extended into the anode contact hole to cover the side surface of the bank structure, an anode of a light emitting element, on the first insulating layer and in the emission area, the anode including first and second conductive layers facing each other in the emission area, an organic anode planarization layer between the first and second conductive layer in the emission area, and a second insulating layer covering an edge of the anode and in which an opening is defined overlapping the anode contact hole, the second insulating layer contacting the first insulating layer.

A method of driving a sensor layer of an electronic device includes, at a first time, driving a first connection line with a first signal, the first connection line connected to a first end of each of first electrodes, driving a second connection line with the first signal, the second connection line connected to a second end of each of first group electrodes of the first electrodes, and driving a third connection line with a second signal different from the first signal, the third connection line connected to a second end of each of second group electrodes of the first electrodes, and generating a magnetic field with the first connection line, the first group electrodes, and the second group electrodes to charge a RLC resonance circuit of a pen at a first time.

A display device includes a display panel having a display area in which a plurality of pixels are arranged; a gate driver configured to drive gate lines in the display area; a data driver configured to drive data lines in the display area; a timing controller configured to align input image data according to a resolution of the display area and control driving timings of the gate driver and the data driver; and a data correction processor configured to obtain an average power consumption for image data in a preset unit of at least one frame, correct the input image data using luminance modulation data according to the average power consumption, and provide corrected image data to the data driver.

A display panel includes upper pixels and lower pixels, each including: a first sub-pixel, which emits first light; a second sub-pixel, which emits second light; and a third sub-pixel, which emits third light having a wavelength longer than that of the first light and shorter than that of the second light. A distance between two closest first sub-pixels is defined as a first distance, a distance between two closest second sub-pixels is defined as a second distance, and a distance between two closest third sub-pixels is defined as a third distance. The first distance and the second distance are each shorter than the third distance, an internal region is defined between the two closest third sub-pixels, and no light or fourth light is emitted from the internal region, and the fourth light is different from the first, second and second lights.

A display device (10) includes: a plurality of subpixels (SP11, SP12, SP13, SP21, SP22, SP23); a plurality of data lines (DL11, DL12, DL13, DL21, DL22, DL23) electrically connected to the plurality of subpixels (SP11, SP12, SP13, SP21, SP22, SP23); a plurality of data pads (DP1, DP2, DP3) electrically connected to the plurality of data lines (DL11, DL12, DL13, DL21, DL22, DL23); a plurality of test pads (TP1, TP2) including a first test pad (TP1) and a second test pad (TP2), the first test pad (TP1) and the second test pad (TP2) being spaced from the plurality of data pads (DP1, DP2, DP3); a first group demux switch element (GDEMT1) connecting a first group data line of the plurality of data lines (DL11, DL12, DL13, DL21, DL22, DL23) to the plurality of data pads (DP1, DP2, DP3); a second group demux switch element (GDEMT2) connecting a second group data line of the plurality of data lines (DL11, DL12, DL13, DL21, DL22, DL23) to the plurality of data pads (DP1, DP2, DP3); and a first test switch element (TET1) located between a first electrode (DEMSD111) of any one of first demux switch elements (DEMT1) included in the first group demux switch element (GDEMT1) and the first test pad (TP1).

A display device includes a display unit including a plurality of pixels, a gate driver including a plurality of stages connected to the plurality of pixels, the plurality of stages comprising a first stage and a second stage. A first gate power line and a second gate power line are configured to be commonly supplied with a first voltage. A reference gate power line is supplied with a second voltage lower than the first voltage. The first stage comprises a ninth transistor including a first electrode connected to the first gate power line, the first electrode configured to receive the first voltage through the first gate power line, and a second electrode connected to an output terminal of the first stage, and a tenth transistor including a first electrode connected to the output terminal of the first stage and a second electrode connected to the reference gate power line. The second stage comprises a ninth transistor including a first electrode connected to the second gate power line, the first electrode configured to receive the first voltage through the second gate power line, and a second electrode connected to an output terminal of the second stage, and a tenth transistor including a first electrode connected to the output terminal of the second stage and a second electrode connected to the reference gate power line.

The invention pertains to an organic molecule for optoelectronic devices. According to the invention, the organic molecule has a structure of formula I: <img class="EMIRef" id="14bd1061-c3ce-4ba6-a917-05e9973974ae-ia01" /> wherein T, V and W are independently from another selected from the group consisting of R<1> and R<2>; R<1> is at each occurrence comprising or consisting of a structure of formula II: <img class="EMIRef" id="14bd1061-c3ce-4ba6-a917-05e9973974ae-ia02" /> which is bonded to the structure of formula I via the position marked by the dotted line; and Z is at each occurrence independently from another selected from the group consisting of a direct bond, CR<3>R<4>, C=CR<3>R<4>, C=O, C=NR<3>, NR<3>, O, SiR<3>R<4>, S, S(O) and S(O)<2> and ring Ar<1> is at each occurrence independently from each other C<6>-C<60>-aryl, which is optionally substituted, and R<2> is independently selected from the group consisting of hydrogen, deuterium, OPh, SPh, CF<3>, CN, F, Si(C<1>-C<5>-alkyl)<3>, Si(Ph)<3>, C<1>-C<5>-alkyl, C<1>-C<5>-alkoxy, C<1>-C<5>-thioalkoxy, C<2>-C<5>-alkenyl, C<2>-C<5>-alkynyl, C<6>-C<18>-aryl, C<3>-C<17>-heteroaryl, N(C<6>-C<16>-aryl)<2>, N(C<3>-C<17>-heteroaryl)<2>; and N(C<3>-C<17>-heteroaryl)(C<6>-C<18>-aryl).

A display device includes a plurality of lower insulating layers on a substrate, a light-emitting element on the lower insulating layers, an encapsulation layer on the light-emitting element and including a plurality of insulating encapsulation layers, a base insulating layer on the encapsulation layer, a conductive pattern on the base insulating layer, and an upper insulating layer on the conductive pattern. The upper insulating layer is spaced from an edge of the substrate. At least one insulating layer among the lower insulating layers, the encapsulation layer, and the base insulating layer extends to the edge of the substrate. A first surface roughness of a first upper surface of the at least one insulating layer, without being covered by the upper insulating layer, is greater than a second surface roughness of a second upper surface of the at least one insulating layer covered by the upper insulating layer.

A display device includes: a substrate including a first display area, a second display area including a light-transmitting part, and a third display area between the first and second display areas; a first subpixel including a first TFT on the first display area and a first light-emitting element on and electrically connected to the first TFT; a second subpixel including a second TFT on the third display area and a second light-emitting element, which is on the second display area and does not overlap with the second TFT in a plan view; a thin-film encapsulation layer on the first and second subpixels,; and a first transparent conductive layer between the second TFT and the second light-emitting element to electrically connect the second TFT and the second light-emitting element. The thin-film encapsulation layer has a refractive index of about 1.5 to about 1.7.

A manufacturing method of a display device according to an embodiment includes forming a bank separating a first opening, a second opening, and a third opening on a first substrate, forming a scatterer layer in the first opening, the second opening, and the third opening, forming a first ink layer in the first opening, forming a second ink layer in the second opening, and forming a third ink layer in the third opening.