Qorvo US

Reducing equivalent series resistance (ESR) of a power management circuit during single transmission is disclosed. The power management circuit includes multiple power amplifier circuits each configured to amplify a signal for transmission. The power management circuit includes a main multi-level charge pump (MCP), a first voltage modulation circuit, a lightweight MCP, and a second voltage modulation circuit. When only one of the power amplifiers is active to amplify the signal for single transmission, the power management circuit will opportunistically couple the main MCP, the first voltage modulation circuit, the lightweight MCP, and the second voltage modulation circuit to the active power amplifier. As such, the active power amplifier will see a reduced ESR that is collectively presented by the main MCP, the first voltage modulation circuit, the lightweight MCP, and the second voltage modulation circuit, and can thus operate with improved efficiency during the single transmission.

A regulated adaptive constant on-time (ACOT) boost converter is disclosed. Herein, the regulated ACOT boost converter includes a synchronous boost converter that can boost an input voltage to a higher output voltage in accordance with a duty cycle. The regulated ACOT boost converter also includes a well-known ACOT controller that determines the duty cycle with repeating cycles each consisting of a fixed on-time duration and a flexible off-time duration. Understandably, for the synchronous boost converter to operate efficiently, the input voltage needs to be lower than the output voltage. In this regard, in an embodiment, the regulated ACOT boost converter can further include a regulating circuit that can cause a dynamic adjustment to the duty cycle when the input voltage is approaching the output voltage. As a result, it is possible to keep the output voltage in regulation and prevent damage in the synchronous boost converter.

A method for processing a RF signal. The method includes receiving the signal having a sequence of chips, sampling the signal to generate a sampled signal, generating, based on the sequence of chips, a cancellation signal, subtracting the cancellation signal from the sampled signal to generate a cancelled signal, and performing an accumulation based on the cancelled signal to generate a channel impulse response (CIR) estimation.

Systems and methods of assessing a plausibility of a ranging measurement are provided. In some embodiments, a method of assessing a plausibility of a ranging measurement includes: obtaining the ranging measurement from a remote device; obtaining one or more measurements associated with the ranging measurement; and based on the one or more measurements associated with the ranging measurement, determining the plausibility of the ranging measurement. The embodiments disclosed herein determine the reliability of the measured range and thus enforce the security level of Ultra-WideBand (UWB) transactions to be secured. Some embodiments are based on existing and standardized metrics. Some embodiments include a capability to auto-assess whether it is reliable to estimate the plausibility of the transaction range. In some embodiments, the computations needed are relatively simple and can be performed by relatively simple devices.

Cable failure protection and battery kickstart in an electronic device is provided. When the electronic device is attached to an external power supply via a universal serial bus type-C (USB-C) cable, it is important to protect the electronic device from being damaged by a cable failure (e.g., overcurrent, overtemperature, and/or faulty cable). Additionally, when a battery in the electronic device is fully depleted, it is necessary to kickstart recharging of the depleted battery upon attaching to the USB-C cable. Herein, a power management integrated circuit (PMIC) is provided in the electronic device and configured in accordance with the USB-C standard to protect the electronic device from the cable failure and kickstart recharging of the depleted battery. By integrating cable failure protection and battery kickstart functionalities into the PMIC, it is possible to reduce cost and footprint of the PMIC, thus making the PMIC suitable for small formfactor electronic devices.

A method for an electronic device to join a downlink-time difference of arrival (DL-TDoA) network as an ad hoc anchor device is provided. The method includes, determining a location of the electronic device, and determining whether a condition to operate as the ad hoc anchor device in the DL-TDoA network is satisfied. The method also includes, in response to the condition being satisfied, transmitting a request message to operate as the ad hoc anchor device in the DL-TDoA network to a server device.

A method for forming a BAW device. The BAW device includes forming a dielectric layer over a reflector structure, forming an electrode seed material layer over the dielectric layer, forming an electrode material layer over the electrode seed material layer, patterning the electrode material layer to form an electrode layer and to expose the reflector structure, and forming a connection layer in contact with the electrode layer and the reflector structure.

Power amplifier circuitry is disclosed having an inverse Class-D amplifier functioning as a power amplifier and self-biasing circuitry generating gate bias voltages for switching type power transistors within the power amplifier. The self-biasing circuitry includes a low-dropout regulator that generates and applies a gate bias voltage in response to a feedback current scaled according to the power amplifier's operating current. A current-based digital-to-analog converter is configured to generate the reference current based on a received digital value. Additionally, a digital processor is configured to generate the digital value in response to the gate bias voltage. The power amplifier circuitry enhances performance and efficiency while ensuring precise control over power transistors' operation, offering advantages for various applications requiring radio frequency signal amplification.

The present disclosure relates to electrostatic discharge (ESD) protection circuitry of an electronic device, which is capable of protecting thin-oxide metal-oxide-semiconductor (MOS) transistors within the electronic device during an ESD event and/or a power-on transient stage without large current leakage. The disclosed ESD protection circuitry at least includes a protection switch and a switch controller. The protection switch is coupled between an external pin of the electronic device and internal circuitry of the electronic device, which is composed of thin-oxide MOS transistors. The switch controller is configured to control the protection switch to be conducting or non-conducting based on both a status of a first voltage supply powering the ESD protection block and a presence of an ESD event at the external pin, such that the external pin is electrically connected to or disconnected from the internal circuitry.

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