Intel

Techniques for tag checking for dynamically repeating memory accesses are described. In an embodiment, an apparatus includes instruction decoder circuitry to decode a single instruction, the single instruction having a format including an opcode field, the single instruction having a first opcode value in the opcode field; and execution circuitry coupled to the instruction decoder circuitry, the execution circuitry to perform operations in response to decoding of the single instruction, the operations including performing repeating memory tag checking operations in connection with repeating memory access operations.

An apparatus and method including: graphics processing cores to execute a mesh shader to process a triangle list associated with a mesh and generate a corresponding tristrip; clipper circuitry to clip the tristrip to a view volume, the clipper circuitry to: read corresponding header data including render target array index (RTAI) and view port index (VPI) values corresponding to a current vertex of the tristrip; perform a vertex cache lookup to determine corresponding RTAI and VPI values associated with a previously processed vertex, if any; read vertex data corresponding to the current vertex from memory and processing with new VPI and RTAI values when the RTAI and VPI values of the current vertex do not match those of a previously processed vertex; and perform clip operations based on previously processed vertex data when the RTAI and VPI values of the current vertex match those of the previously processed vertex.

Techniques are provided herein to form an integrated circuit having backside conductive contacts (238/240) as part of a gate tie-down structure. Backside cavities beneath a gate structure and an adjacent source region (106b) may be formed using backside lithography and anisotropic etching. The backside cavities are subsequently filled with a conductive material to form the backside contacts. A semiconductor device includes a gate structure around (108) or otherwise on a semiconductor region (104) that extends from a first source region to a second source or drain region. The substrate beneath the semiconductor device is removed and replaced with a backside dielectric material (130). Lithographic operations may be performed on the backside dielectric material along with one or more anisotropic etches to form a first cavity beneath the gate structure and a second cavity beneath the first source region. The backside conductive contacts are then formed within the backside cavities.

An apparatus and method for progress tracking strided vector loads and stores. For example, an example method comprises: decoding a progress tracking strided load instruction including fields to indicate a destination vector register in which to load source data elements, memory locations of the source data elements, and a register to store a progress indication; initiating execution of the progress tracking strided load instruction; loading one or more of the source data elements to corresponding locations in the destination vector register; updating the progress indication in accordance with the one or more source data elements loaded or a next source data element to be loaded; and in response to an interruption of the execution of the progress tracking strided load instruction, re-starting the execution of the instruction from an execution point based on the progress indication.

Systems, apparatus, articles of manufacture, and methods to compensate for impedance and reduce crosstalk in integrated circuit packages are disclosed. An example apparatus includes a metal interconnect within a substrate of an integrated circuit package. The metal interconnect includes a contact pad in a first metal layer of the substrate and a via pad in a second metal layer of the substrate. The metal interconnect defines a conductive path for an electric signal that is to pass through both the contact pad and the via pad. The example apparatus further includes a conductive material having a length defining a segment of the conductive path between the contact pad and the via pad. At least a portion of the length of the conductive material extends along a course that corresponds and is adjacent to a portion of a perimeter of the contact pad.

Systems and methods for providing a temporal noise reducer (TNR) architecture that improves TNR performance by adjusting for lighting differences between image frames. Temporal noise reduction is a core feature of a video processing pipeline, where TNR can be used to decrease noise in video streams. Some TNRs compensate for the motion of objects between frames, but lighting changes can also lead to additional noise. As an object's position moves from frame to frame, the lighting of the object may change. A lightweight tone-mapping and color-correction operator is added to the TNR feedback loop, matching the radiometric properties of a TNR reference frame to the radiometric properties of the current frame to compensate for radiometric differences, thereby increasing the effectiveness of TNR in handling incremental lighting changes and speeding up its response to abrupt lighting changes.

A processor or other apparatus of an aspect includes a cache to store cache lines and a circuitry coupled with the cache. The circuitry is to receive a memory access request for data at a memory address from a first security domain. The data at the memory address is to be shared by a plurality of security domains including the first security domain. A side-channel protection is to be used for the data. The circuitry is to implement the side-channel protection for the data. This includes not providing a cache line corresponding to the memory address from the cache to the first security domain, when the cache line exists in the cache and is valid, if the first security domain has not previously accessed the cache line in the cache. Other processors, methods, systems, and instructions are disclosed.

An example processor includes vector registers to store sub-matrices of two source matrices and execution circuitry to perform a cross-product matrix multiplication. A decoder interprets an instruction specifying the source matrices and the operation. The execution circuitry multiplies each combination of sub-matrices from the two source matrices-first with first, first with second, second with first, and second with second-to generate four corresponding sub-matrices of a result matrix, which are stored in a third vector register. This architecture enables efficient parallel matrix computations for high-performance processing tasks.

An example processor executes an instruction having an operand field to indicate a multi-register cross-product matrix multiplication to be performed with the first plurality of sub-matrices and the second plurality of sub-matrices to generate the third plurality of sub-matrices. Execution circuitry execute the instruction, the execution circuitry to generate each sub-matrix of the third plurality of sub-matrices in a corresponding vector register of the third plurality of vector registers by multiplying a sub-matrix in a corresponding vector register of the first plurality of vector registers and a sub-matrix in a corresponding vector register of the second plurality of vector registers.

Techniques are provided herein to form semiconductor dies (or integrated circuits) with a thermally conductive layer adjacent to a bond interface to enhance the thermal dissipation from the semiconductor devices. A semiconductor die or integrated circuit includes any number of semiconductor devices within a device layer. A frontside interconnect region is provided above the device layer to, for example, route signals between the various semiconductor devices in the device layer. A thermally conductive layer may be provided above the frontside interconnect region, such as on a top-most layer of the frontside interconnect region. The thermally conductive layer includes a material having a thermal conductivity of, for example, at least 1.5 W/m·K. A bond layer may be provided adjacent (e.g., directly above or directly below) the thermally conductive layer and may be any suitable dielectric material, such as silicon dioxide.