Pjanovic, Ilija

A goal of the current disclosure is to provide a module for electric circuitry having lower parasitic inductance. This is achieved because in an example, the module for an electric circuit comprises a substrate comprising electric circuitry containing a Direct Current, DC, pad and an Alternating Current, AC, pad. In particular, a first group of semiconductor dies is mounted on the AC pad, whereas a second group of semiconductor dies is mounted on the DC pad. Furthermore, the module comprises a first DC terminal electrically connected to the first group of semiconductor dies, a second DC terminal being electrically isolated from the first DC terminal, and at least electrically connected to the DC pad of the electric circuitry, and an Alternating Current, AC, terminal at least connected to the AC pad of the electric circuitry. Also, the module comprises first connecting means for electrically connecting the first group of semiconductor dies to the AC pad, second connecting means for electrically connecting the second group of semiconductor dies to the DC pad, and third connecting means for electrically connecting the second group of semiconductor dies to the AC pad.

The object of the present disclosure is to provide semiconductor assembly allowing to avoid cutting of the lead frame while separating the adjacent semiconductor assemblies, and allowing to perform sawing of the assemblies before trimming off the leads, for small packages. According to the first aspect, the object of the present disclosure has been achieved by providing a semiconductor assembly comprising a semiconductor die held in an encapsulant, wherein the encapsulant has a top part and a bottom part with leads extending out of the two opposite sides of the bottom part, wherein the bottom part of the encapsulant has a smaller width than the top part of the encapsulant, when measured along the lead bearing surfaces of the encapsulant. Providing a bottom part narrower than the top part allows for partial package sawing, where only the top part of the encapsulant is cut and cutting of the lead frame is avoided.

A method of manufacturing a semiconductor package assembly and a semiconductor package is provided, with integral electrically conductive layers seeded on the first die side and on the part of the at least one lead frame terminal.

A continuous time comparator, comprising a first Field Effect Transistor, FET, (Mn1) arranged for receiving a first input signal, and a second FET (Mn2) arranged for receiving a second input signal, two branches, a first of said two branches comprises a first transistor (Mp1) and a second of said two branches comprises a second transistor (Mp2), wherein said first of said two branches is connected to said first FET (Mn1) and wherein said second of said two branches is connected to said second FET (Mn2), a first dynamic clamp circuitry connected in parallel over said first branch, wherein said first dynamic clamp circuitry is arranged to dynamically clamp a voltage at a gate of a first output transistor (Mp4), and a second dynamic clamp circuitry connected in parallel over said second branch, wherein said second dynamic clamp circuitry is arranged to dynamically clamp a voltage at a gate of a second output transistor (Mp3), said first and second output transistors (Mp3, Mp4) for providing an output of said comparator and for providing an inverting output of said comparator.

An ElectroStatic Discharge, ESD, protection device for protecting an integrated circuit, said ESD protection device comprising a two-stage protection circuit arranged to be connected to an input of the integrated circuit, wherein the two-stage protection circuit comprises a first protection stage connected to an external input and to ground, wherein the first protection stage is arranged for, when triggered, providing a low ohmic path to said ground, an impedance connected to the external input and arranged to be connected to the input of the integrated circuit, a second protection stage arranged to be connected to the input of the integrated circuit and connected to ground, wherein the second protection stage is arranged for, when triggered, providing a low ohmic path to said ground, a triggering mechanism arranged for triggering the second protection stage with the first protection stage.

A method for manufacturing a semiconductor device is proposed, the method comprising: a) providing a lead frame structure with a first lead frame surface and an opposite second lead frame surface, where the lead frame structure comprises an outer frame, an at least one lead frame die pad, an at least one lead frame terminal, and the plurality of lead frame junctions. The at least one lead frame die pad and/or the at least one lead frame terminal are accommodated in a floating orientation within the lead frame structure; b) providing a pre-binding material for fixing the floating lead frame die pads and/or floating lead frame terminals within the lead frame structure; c) mounting an at least one semiconductor die on the at least one lead frame die pad; d) mounting an at least one connecting element for creating an electrical connection between the at least one semiconductor die and the at least one lead frame terminal, e) encapsulating by a mold compound the lead frame structure, the at least one semiconductor die, the at least one connecting element and the pre-binding material to form the semiconductor device, such that at least part of the at least one lead terminal is exposed and thereby forming an encapsulated semiconductor device. According to the second aspect of the disclosure, there is provided a semiconductor device as manufactured in accordance with the method according to the disclosure.

The present disclosure provides a semiconductor package comprising: a semiconductor die attached to a lead frame having lead terminals; at least one bond clip connecting the die to a lead terminal; a die top solder connecting the bond clip and the die, and an encapsulant. The clip comprises a die attachment portion having a die attachment portion side structured to be connected to the die, whereby said side is provided with a cavity functioning as an expansion space for the die top solder. This allows to prevent the molten die top solder from spreading toward die edge and lead terminals, since the molten solder flow is directed inward to the cavity, instead of flowing outward. A bond clip for use in a semiconductor package is also provided, comprising a cavity functioning as an expansion space for the die top solder. The cavity is arranged at the die attachment portion side of the bond clip.

A semiconductor device and a semiconductor package including such semiconductor device are presented. The semiconductor device includes one or more dies, a power source clip, a signal source clip, a signal gate clip and a power drain clip, with each clip electrically connected to each of the dies. A Kelvin source connection is integrated on the signal source clip. At at least one of the dies an angle between a path of a power source current between the power source clip and a die and a path of a signal source current between the signal source clip and the die is equal to or larger than 90°.

An encapsulated semiconductor package is proposed, comprising a plurality of rivets, and a plurality of connection pins, each connection pin having a pin tip and a pin end, wherein the plurality of rivets are disposed in the encapsulant of the encapsulated semiconductor package, each rivet having a first rivet end and a second rivet end, each rivet being electrically mounted with a first rivet end on a corresponding bond pad of the semiconductor package; each rivet comprises a rivet cavity configured to receive the pin tip of the connection pin; the pin tip of the connection pin is configured as a press-fit pin tip having an outer diameter larger than an inner diameter of the rivet cavity and configured for friction-based engagement with the rivet cavity.

According to a first example of the disclosure a single cell lateral oriented Metal-Oxide-Semiconductor device is proposed. The device comprises a semiconductor comprising a first surface; a first region having a first conductivity type; an at least one pair of trenches, wherein each trench extends from the first surface into the first region, each of the trench comprising an insulating element and a conductive element, wherein the insulating element is arranged in between the conductive element and the first region, and wherein the insulating element has a substantially uniform width; a second region having a second conductivity type being different from the first conductivity type, wherein the second region extends from the first surface into the first region and is located on an outer side of the pair of trenches and adjacent to the trench, and a third region having a second conductivity type being different from the first conductivity type, wherein the third region extends from the first surface into the first region and is located in between trenches and adjacent to the trench, and an insulating region on the first surface comprising openings to provide electrical contacts to the second and third region.This disclosure also relates to a method of manufacturing a lateral oriented Metal-Oxide-Semiconductor device.