Avago Technologies International Sales Patente

An apparatus including first and second samplers, first and second analog-to-digital converters, and a clock generator. The first sampler produces a first stream of sampled values in response to sampling an analog input signal on a first input channel. The first analog-to-digital converter generates a first stream of digital data. The second sampler produces a second stream of sampled values in response to sampling an analog input signal on a second input channel. The second analog-to-digital converter converts the second stream of sampled values into a second stream of digital data. The clock generator causes the first analog-to-digital converter to convert the first stream of sampled values into the first stream of digital data in response to a mode instruction designating a custom operating mode. The clock generator also causes the first analog-to-digital converter to convert the second stream of sampled values into the first stream of digital data in response to the mode instruction designating a standard operating mode.

A computer is configured to set up a remote direct memory access (RDMA) connection for an application, by performing the steps of: receiving, from the application, by an RDMA driver, a sequence of API requests for setting up the RDMA connection, the API requests including information for setting up the RDMA connection; transmitting, by the RDMA driver to a NIC of the computer, in response to a last API request in the sequence, a first hardware request for setting up the RDMA connection; and generating, by the NIC in response to the first hardware request, a queue pair based on the information for setting up the RDMA connection, and also configuring, by the NIC, the queue pair based on the information for setting up the RDMA connection, the queue pair including memory space for storing receive and send requests of the application.

Cooling assemblies that can be used with various types of integrated circuits to provide improved efficiency. An example integrated circuit includes a circuit die, a stiffener ring, a heat exchange structure, and a cover plate disposed on the heat exchange structure; and a clamp secured to the cover plate. The integrated circuit can also include a seal disposed between the cover plate and the heat exchange structure, where the seal prevents leakage of fluid that circulates through the heat exchange structure.

The subject technology is directed to semiconductor devices and fabrication methods thereof. In an embodiment, the subject technology provides an apparatus that includes a substrate comprising a first metal material and a first layer coupled to the substrate. The apparatus further includes a second layer coupled to the substrate via the first layer. The second layer comprises an organic material. The first layer includes a third layer comprising a first adhesion material configured to couple to the organic material, a fourth layer comprising a second adhesion material, and a fifth layer comprising a third adhesion material configured to couple to the first metal material. The multi-layer adhesion system enables reliable bonding between organic and metallic components, ensuring robust mechanical and electrical performance of the system. There are other embodiments as well.

A wireless device may include a transmitter and one or more processors. The processors may be configured to receive a plurality of spatial streams of encoded data corresponding to a number of spatial streams. The processors may be configured to modulate encoded bits of the encoded data to a set of modulated symbols using a number of bits per subcarrier stream (NBPSCS). The processors may be configured to determine a tone-mapping distance based at least on the number of spatial streams and the NBPSCS. The processors may be configured to map the set of modulated symbols onto a set of frequency subcarriers using the determined tone-mapping distance. The transmitter may be configured to transmit the encoded data to another wireless device using the set of frequency subcarriers.

Equal probability dynamic element matching functionality for use in various types of integrated circuits (e.g., communications circuits, etc.). The equal probability dynamic element matching functionality generally includes arranging circuit elements in a loop, and using both a pointer and a random number having a binary value to provide equal selection of circuit elements in the loop over time. The equal probability dynamic element matching functionality can be used to improve performance and durability of various types of integrated circuits.

An apparatus including a comparator and a plurality of replica current sources. The comparator outputs a control voltage onto an output line upon comparing a midpoint voltage with a feedback voltage. The control voltage indicates whether the feedback voltage is higher or lower than the midpoint voltage. Each of the replica current sources draws a supply voltage from a supply line. A replica current source enters into an inactive state in response to an enable signal being in a deactivating state. Upon entering the inactive state, the replica current source ceases drawing the control voltage from the output line.

The disclosure describes systems and methods for implementing network slicing in optical access networks. The system can identify a plurality of allocation identifiers corresponding to a plurality of optical network units in a passive optical network. Each of the plurality of allocation identifiers can have one or more properties. The system can establish one or more slices, where each of the one or more slices can include a set of allocation identifiers of one or more flows having a common property of the one or more properties. The system can allocate a portion of bandwidth to each of the one or more slices. The system can associate the one or more slices with one or more virtual network operators.

A circuit including a first resistor (R21), a second resistor (R22), a current source (211) and a transistor (QP23). The first resistor (R21) is between a voltage rail and a drive interconnect. The drive interconnect and the voltage rail are electrically connected to the first resistor (R21). The second resistor (R22) is between the drive interconnect and ground. Ground and the drive interconnect are electrically connected to the second resistor (R22). The current source (211) is between the voltage rail and the drive interconnect. The drive interconnect and the voltage rail are electrically connected to the current source (211). The transistor (QP23) is between the drive interconnect and a sink interconnect. The drive interconnect and the sink interconnect are electrically connected to the transistor (QP23).

Compact mechanisms for attaching co-packaged devices to integrated circuit (IC) packages. An example integrated circuit includes a substrate having an outer periphery; a circuit die disposed on the substrate and contained within the outer periphery; a stiffener structure that is disposed on the substrate, contained within the outer periphery, and including a threaded opening; a compression structure secured to the stiffener structure via the threaded opening; and a co-packaged device (CPD) disposed on the substrate such that a first surface portion of the CPD contacts the compression structure and such that a second surface portion of the CPD contacts the substrate.

A digital pre-distortion circuit and technique for a signal being amplified. Digital pre-distortion is performed using a model-based pre-distortion function. Pre-distortion is further corrected using a data-driven pre-distortion function. The model-based pre-distortion function and the data-driven pre-distortion function are trained using training data including a digital loopback signal generated by sampling a loopback signal of an amplifier, the digital pre-distorted signal input to the amplifier for a time period, and an intermediate signal output from the model-based pre-distortion function driven by the digital loopback signal or an output of the data-driven pre-distortion function. Parameters may be continually updated in order to account for changes in characteristics of the amplifier.

An assembly including a capacitive height sensor and a conditioning circuit. The capacitive height sensor detects capacitance between a read/write head and a disk surface to monitor variances in a flying height. To bring about a measurement voltage between the capacitive height sensor and the disk surface, the conditioning circuit supplies a drive current to the capacitive height sensor. The conditioning circuit ceases flowing the drive current to the capacitive height sensor upon detecting that the measurement voltage is greater than a high threshold, and commences flowing the drive current to the capacitive height sensor upon detecting that the measurement voltage is less than a low threshold.

The systems and methods for providing interference mitigation for a multiband wireless communication system are disclosed. A device can include wireless transceivers operating on different bands and a circuitry to receive a first signal via a first band and transmit a second signal via a second band. The second signal can cause an interference with the first signal. The interference can include a central portion and a tail portion. A filter can reduce, from a sample of the second signal, the central portion of the interference to provide a filtered sample signal, whose carrier frequency can be adjusted to a different carrier frequency or baseband to provide a converted sample signal. An equalizer can identify, from the converted sample signal, the tail portion of the interference to provide a third signal, which a demodulator can use to reduce the interference from the first signal.

The subject technology is directed to clock calibration systems and methods. In an embodiment, the subject technology provides an apparatus for clock calibration to minimize timing discrepancies between even and odd clock edges. The apparatus includes a first data path configured to generate a first signal, the first signal comprising a first edge and a second edge associated with even and odd clock cycles, respectively. A calibration circuit is coupled to the first data path and configured to determine a timing difference between the first edge and the second edge to calculate even-odd jitter (EOJ). This configuration enables precise calibration to reduce EOJ and ensure accurate synchronization of clock signals in high-speed communication systems.

A terminal including a transceiver, an analog-to-digital converter and control circuitry. The transceiver receives a stream of bursts from a plurality of units. One of the units is an electronic device. The analog-to-digital converter receives an upstream burst from the transceiver during an active time slot. The upstream burst is one of the bursts. In response to sampling the upstream burst at a sample rate, the analog-to-digital converter converts the upstream burst from an analog waveform into a sequence of digital values. In response to a coefficient for the electronic device being a default coefficient, the control circuitry stores the digital values into memory during the active time slot.

Methods and systems for adjusting phase lock loop devices. In a specific embodiment, the subject technology provides a system that includes a sampler for generating samples from a first data stream and a clock and data recovery (CDR) circuit to determine phase offset and generate a first control code. The system also includes a phase interpolator produces a first clock signal based on the first control code and a second clock signal. The system includes a first filter configured to track the phase interpolator movement, and it generates a second control code that includes a fractional divider value. The system includes a phase-locked loop (PLL) circuit that uses a reference clock to generate the second clock signal based on the third clock signal and the second control code. There are other embodiments as well.

A method for improving wafer-level optical characteristic uniformity. The method includes forming a first layer of dielectric overlying the first wafer and a second layer of dielectric overlying the second wafer. The method also includes measuring a refractive index distribution of the second layer and measuring a first thickness distribution of the first layer. The method also includes determining a second thickness distribution for the first layer based on the refractive index distribution and the first thickness distribution. The method further includes removing material nonuniformly and selectively from the first layer based on the second thickness distribution, resulting in a third layer in the second thickness distribution characterized by a spectral response with a characteristic wavelength uniformity better than +/- 2.5 nm across the first wafer.

An optical receiver unit (110) is described, the unit comprising: an anode terminal (PDA) configured to be connected to an anode of a photodiode, a cathode terminal (PDK) configured to be connected to a cathode of the photodiode, a transimpedance amplifier (TIA) having an input and an output, a first electrically conductive structure (112) coupling the anode terminal to the input, and a second electrically conductive structure (114) coupling the cathode terminal to a bias voltage supply (LDO), the second electrically conductive structure comprising two conductive lines (1141, 1142) extending on opposite sides of the first electrically conductive structure. Furthermore, an optical receiver module comprising a plurality of such units and a method of manufacturing the units are described.

Method and system for direct memory access. According to an embodiment, the subject technology provides a system for facilitating memory address translation in a virtualized computing environment to enable efficient access to a graphics processing unit (GPU) by a virtual machine. The system includes a host machine equipped with a host tool configured to obtain and map address translations between a first memory address associated with the virtual machine and a second memory address associated with GPU memory. The host tool provides a mapping table containing these address mappings. A communication link is configured to transfer the mapping table from the host machine to the virtual machine. Within the virtual machine, a driver for a network communication device receives the mapping table and provides the second memory address to another address mapping table on the network communication device.

A media access control layer (MAC) or device for shared bus network system for collision-less data packet transmission, the media access control layer includes a transmission controller, priority queues, timestamper, and optional coordinator packet generator. The transmission controller is configured to decode a coordination packet received from the physical layer. The transmission controller is further configured to extract control information from the coordination packet. The transmission controller is further configured to generate a data packet transmission schedule and allocate non-overlapping time intervals to transmit the plurality of data packets with collision avoidance.

A system is provided that includes a machine learning (ML) application client configured to monitor data streams communicated with a connected device for application data associated with the ML application client, and to capture the associated application data. An ML proxy client is configured to receive an application request from the ML application client, where the application request includes the application data captured by the ML application client; send a proxy request to an ML proxy server, where the proxy request includes the application data and an indicated inference operation to be performed on the application data; receive a proxy response from the ML proxy server, where the proxy response includes a result of the inference operation performed on the application data; and send a report based on the proxy response to a controller outside the first network.

In an example, a device may include logic to receive a plurality of video frames from a video source, logic to process the plurality of video frames, logic to provide at least some of the plurality of video frames to a video sink, and logic to reduce a display latency of each of the video frames provided to the video sink by decoding and/or processing only portions of some frames.

The subject technology is directed to an apparatus for packet processing in a network. In an embodiment, the apparatus comprises a first port configured to receive a first packet. The apparatus further comprises a processor coupled to the first port, the processor configured to generate a first metadata associated with the first packet and determine a first size of the first metadata. The apparatus also includes a buffer coupled to the processor, which is configured to store the first packet and the first metadata. Based on a determination that the first size exceeds a predefined threshold, the processor is further configured to move a portion of the first packet to accommodate the larger metadata. This configuration allows for dynamic adjustment of packet data and metadata storage, optimizing the handling of packets with varying metadata requirements. There are other embodiments as well.

The subject technology is directed to an apparatus for signal processing. In an embodiment, the apparatus includes a driver configured to receive an input signal comprising a first signal component characterized by a first voltage level and a second signal component characterized by a second voltage level. The apparatus further includes a first circuit configured to adjust the first voltage level by applying a first bias voltage to the first signal component and adjust the second voltage level by applying a second bias voltage to the second signal component. A quantizer is coupled to the driver and configured to generate an output signal based at least on the first voltage level and the second voltage level. This configuration allows for improved signal-to-noise ratio and effective use of the quantizer's dynamic range, enhancing the clarity and accuracy of signal processing in differential systems. There are other embodiments as well.

An example carrier substrate of an integrated circuit (IC) includes: a top surface configured to support a semiconductor die; a bottom surface configured to support solder balls; a plurality of fiducial marks disposed on a surface area comprising at least one of the top surface or the bottom surface, the plurality of fiducial marks comprising metal portions; a first solder resist disposed on the plurality of fiducial marks; and a second solder resist disposed on the surface area other than over the first solder resist, the first solder resist having contrast with respect to the second solder resist.

An apparatus includes a receiver configured to receive data, and circuitry configured to receive one or more symbols based at least on the data, determine, using the one or more symbols, an error vector magnitude (EVM) value, identify a quadrature amplitude modulation (QAM) size, determine, using the EVM value and the QAM size, a signal-to-noise (SNR) value, and adjust, based at least on the SNR value, a transmission rate of a transmitter.

The disclosure describes systems and methods for retaining low-power connections in multilink networks. An access point can include a plurality of radios, each operating on a different frequency band. The access point can establish connections with clients. The access point can receive a frame indicating the connected clients are entering sleep mode. In response, the access point can cause a radio, operating on a longer range and lower power band, to go into sleep mode, while maintaining a lower power connection with the clients. The access point can switch off the other radios operating on higher frequency bands. During a wakeup period, the access point can transmit a beacon via the lower power radio, indicating to the clients that the access point has broadcast and multicast (BCMC) data. The access point can transmit the BCMC data via the low-power radio to the clients.

An example network interface controller (NIC) includes: first resources configured to supply first traffic; second resources configured to supply second traffic; a load balancer, coupled to the first and second resources, configured to balance the first traffic and the second traffic between first and second port circuits of a link aggregation group (LAG) using a hash function; and remote direct memory access (RDMA) logic configured to, using the hash function, divide work requests into a first set of work requests for first packets that hash to the first port circuit and a second set of work requests for second packets that hash to the second port circuit, the RDMA logic configured to supply the first set of work requests to the first resources and the second set of work requests to the second resources.

A digital pre-distortion achieving near ideal spectral regrowth suppression with a bandlimited loopback. To eliminate mismatch between the bandwidth of the pre-distortion model terms and the bandwidth of the signal used to determine the model a band limiting operation may be applied to both the loopback signal and the input to the power amplifier used for estimating the pre-distortion coefficients. In addition, oversampling may be performed in the digital domain to avoid aliasing in the nonlinear terms of the pre-distortion model.

Example methods and network interface devices for congestion control are described. In one example, a network interface device may include a first processing layer and a second processing layer. The first processing layer may receive an event notification from the second processing layer. In response to determination that congestion control is required based on the event notification, the first processing layer may determine an adjustment to a packet forwarding parameter by applying a congestion control algorithm. The congestion control algorithm may be one of multiple congestion control algorithms that the first processing layer is programmable to apply. The first processing layer may generate and send an instruction to the second processing layer to perform the adjustment. Based on the instruction, the second processing layer may configure a component to control packet forwarding towards a physical network based on the second value of the packet forwarding parameter.

In an example, a device may include logic to receive a plurality of video frames from a video source, logic to process the plurality of video frames, logic to provide at least some of the plurality of video frames to a video sink, and logic to reduce a display latency of each of the video frames provided to the video sink by reducing a number of frames in a video pipeline comprising the device.

A module including first and second variable inductances. The first variable inductance is electrically connected to a pair of nodes in a first half-circuit. One of the nodes in the first half-circuit is a first connection terminal. The second variable inductance is electrically connected to a pair of nodes in a second half-circuit. One of the nodes in the second half-circuit is a second connection terminal. The first half-circuit receives a flow of current in response to the second half-circuit supplying the current to the load in a flow direction from a load through the first connection terminal. The second half-circuit is configured to receive the flow of the current in response to the first half-circuit supplying the current to the load in a direction opposite to the flow direction from the load through the second connection terminal.

A network device for capability-based autonomous SAN traffic engineering is provided. The network device includes one or more ingress points configured to receive one or more packets from a first network node, a first set of buffers configured to store packets associated with a first group of network nodes, and a packet processing logic configured to determine a communication speed of the first network node over a first channel, wherein the packet processing logic is configured to assign the first network node to a first group nodes of the plurality of groups of network nodes, and store the one or more packets from the first network node in the first set of buffers.

An electronic circuit including an amplifier, a first variable capacitance and a second variable capacitance. The amplifier receives an input signal across an inverting input terminal of the amplifier and a non-inverting input terminal of the amplifier. The first variable capacitance is electrically directly connected to the output terminal of the amplifier and the inverting input terminal of the amplifier. The second variable capacitance is electrically directly connected to the output terminal of the amplifier and the non-inverting input terminal of the amplifier.

The subject technology is directed to a device for managing inrush current in voltage regulation systems. The device includes an input configured to receive an input voltage and an output configured to provide an output voltage. The device includes a first circuit configured to generate a first signal associated with the output voltage. The device further includes a first comparator configured to compare the first signal with a first reference voltage and generate a second signal based on the comparison. The device further includes a switch configured to receive the second signal and adjust a first resistance in a current path between the input and the output based on the second signal. The device implements multilevel inrush current control, allowing for dynamic adjustment of the inrush current at different stages of the power-up phase.

This application discloses wireless devices, multi-scan PHY blocks thereof, and associated methods. A multi-scan PHY block might include a first number of front-end blocks and a second number of back-end blocks. The multi-scan PHY block might enable detection by the front-end blocks of packets on a plurality of wireless channels and demodulation by the back-end blocks of the packets on the plurality of wireless channels without requiring a separate back-end block for each wireless channel.

In an example, a device may include logic to receive a plurality of video frames from a video source, logic to process the plurality of video frames, logic to provide at least some of the plurality of video frames to a video sink, and logic to reduce a display latency of each of the video frames provided to the video sink by changing the frame rate of some or all of the frames.

The subject technology is directed to an apparatus for managing data packets in a network. In an embodiment, the apparatus comprises a first memory configured to store a plurality of packets. The apparatus further comprises a queue manager configured to receive a plurality of packet descriptors and generate an aggregated packet descriptor based on the plurality of packet descriptors. The apparatus further comprises a traffic manager coupled to the queue manager. The traffic manager is configured to determine a transmission order for the plurality of packets based on the aggregated packet descriptor. A transmitter is coupled to the traffic manager and configured to transmit the plurality of packets based on the determined transmission order. This configuration enables efficient packet storage, aggregation, and transmission scheduling, optimizing overall network performance and resource utilization. There are other embodiments as well.

An example Global Navigation Satellite System (GNSS) receiver includes: an analog front-end (AFE) having analog circuits and configured to observe a GNSS frequency; a first circuit, coupled to the AFE, configured to power on the analog circuits during a first time period to generate a first set of digital samples from the AFE, and power off the analog circuits during a second time period after the first time period; and a digital signal processor (DSP) coupled to the AFE, the DSP configured to be powered on during the first and second time periods and configured to pass the first set of digital samples through functions to generate time delays between transmission of GNSS signals from satellites and reception at the GNSS receiver.

At least one aspect of the technical solutions is directed to a system. The system can include a first access point configured to generate a preamble for a network packet of a wireless local area network (WLAN). The first AP can be configured to include, into the common field of the preamble, one or more basic service sets (BSS) colors associated with the first AP and the second AP. The first AP can be configured to include, into a subfield of the user field for indicating error correction coding, an indication of association of the client device with the first AP or the second AP based on the one or more BSS colors. The first AP can be configured to transmit the network packet to be processed by the client device for CBF communication of the network packet according to the one or more BSS colors and the indication.