Avago Technologies International Sales Patente

Systems for and methods of reducing soft errors can be utilized in any circuit. A circuit can include a first inverter having a first inverter input and a first inverter output, a second inverter having a second inverter input and a second inverter output, and a soft error hardening circuit. The first inverter input is coupled to the second inverter output, and the second inverter input is coupled to the first inverter output. The clock input is configured to receive a clock signal. The soft error hardening circuit is coupled to the first inverter and/or the second inverter.

In some implementations, a device may include a transmitter associated with an access point (AP) corresponding to a basic service set (BSS) selectively operating in one of a first frequency range or a second range. The one or more processors may be configured to determine that the AP operates in the second frequency range. The one or more processors may be configured to determine that the transmitter has a limitation in transmitting using the second frequency range. The one or more processor may be configured to transmit, to the transmitter via the AP, a request to generate a frame including a recommended frequency range that is different from the first frequency range. The one or more processors may be configured to generate the frame including a recommended frequency range. The one or more processors may be configured to transmit, to the AP via the transmitter, the generated frame.

A traffic monitor is configured to alert a second vehicle about a first vehicle in front of the second vehicle, by performing the steps of: broadcasting a first request for speed information as a first Bluetooth Low Energy signal, the first request including a universally unique identifier associated with BLE, and then receiving a first response from the first vehicle in response to the first request, the first response containing data that indicates that the first vehicle is moving at a first speed; comparing the first speed to a threshold speed to determine that the first speed is less than the threshold speed, and determining, based on the first speed, a first time period for alerting other vehicles about the first vehicle; and alerting the second vehicle during the first time period about the first vehicle in response to the first speed being less than the threshold speed.

In an example, an apparatus for supplying a voltage to a termination in a receiver, the circuit includes: a first circuit coupled to a current source through a first resistor; first and second inverters coupled between a supply voltage and a first node between the first resistor and the current source; second and third resistors; first and second transistors, gates of the first and second transistors coupled to outputs of the first and second inverters, respectively, drains of the first and second transistors coupled to a second node, sources of the first and second transistors coupled to a third node through the second and third resistors, respectively; wherein the first circuit is coupled to the third node and the second node is configured to supply the voltage to the termination in the receiver.

An apparatus including a host and a controller. The host sets a binary value for metadata in a field of a command structure. In response to receiving a stream of write commands from the host, the controller parses the command structure in write command. The write command is one of the write commands in the stream. The command structure extracts the binary value from the metadata. From the binary value, the controller derives a proximity of the write command relative to another write command in the stream.

An example surface mount device (SMD) includes: an enclosure having contacts; first and second inductors disposed in the enclosure, the first inductor including a first coil electrically coupled between first and second ones of the contacts, the second inductor including a second coil electrically coupled between third and fourth ones of the contacts; the first coil including first conductors disposed on layers in the enclosure, the first conductors being electrically coupled; the second coil including second conductors disposed on the layers in the enclosure, the second conductors being electrically coupled; wherein each dimension of the first and second contacts is less than a corresponding dimension of the first coil and each dimension of the third and fourth contacts is less than a corresponding dimension of the second coil.

A circuit including a first input, a photodetector, and a single ended to differential converter. The first input is to receive a transmission pulse. The photodetector is to receive a reflected light pulse. The single ended to differential converter includes a second input and an output. The second input is electrically connected to the first input and the photodetector. The output outputs an electrical signal comprising a first signal based on the transmission pulse and a second signal based on the reflected light pulse.

In an example, an apparatus in a network switch can include processing pipelines including outputs coupled to a switch circuit of the network switch; a first circuit coupled between port groups of the network switch and inputs of the processing pipelines, the first circuit configured to distribute packets output from the port groups among the processing pipelines; and a memory coupled to the processing pipelines; wherein the processing pipelines are configured to process streams of the packets through digital logic based on state for the port groups to generate results, supply the results to the switch circuit to switch the packets, and write and read the state to and from the memory.

A power transceiver includes a current sense circuit, a ballast actuator and a ballast regulator. In response to measuring an amount of rectified current flowing along a pathway from an input terminal to an output terminal, the current sense circuit generates a sense signal that indicates the amount of the rectified current. The ballast actuator draws an amount of a ballast current from the rectified current from the output terminal. The ballast regulator performs a comparison of the sense signal with a reference signal. In response to the comparison indicating that the rectified current is at or above a transition point where a current level of the rectified current reaches a shift current, the ballast regulator triggers the ballast actuator to decrease the amount of the ballast current drawn from the output terminal.

Devices, systems, and methods that utilize an optical medium efficiently, for example by performing bidirectional (BiDi) dense wavelength division multiplexing (DWDM) according to a wavelength plan. Some wavelength plans prioritize or consider radix, energy efficiency, and/or fiber utilization. Some devices can be network devices, such as switches, routers, and/or the like. Some devices can be computers, servers, and/or the like.

The subject technology is directed to clock generation and calibration systems and methods. In an embodiment, the subject technology provides an apparatus that includes a first delay line configured to receive an input clock signal and generate a first clock signal by providing a first delay to the input clock signal. The apparatus further includes a second delay line configured to receive the input clock signal and generate a second clock signal by providing a second delay to the input clock signal. A phase detector is coupled to the first and second delay lines to determine a phase difference between the first and second clock signals. A comparator generates an output signal based on the phase difference, and a controller adjusts the first or second delay based on the output signal. The system enables precise phase alignment and skew calibration for clock signals. There are other embodiments as well.

The present invention generally relates to programmable delay generation techniques, and more specifically, to methods and systems for providing programmable delay for skew adjustment and lane synchronization in high-speed communication systems. A device for generating and aligning clock signals across multiple lanes in a high-speed communication system is disclosed. The device includes a controller providing control signals and a phase-locked loop generating a first clock signal. A first lane within a plurality of lanes comprises a first clock generator producing a first signal pair based on the first clock signal and a phase interpolator generating a second clock signal using the first signal pair and the control signals. The device further includes a circuit coupled to the lanes and configured to align their outputs for synchronization. There are other embodiments as well.

An example apparatus includes a circuit configured to implement a security function; a first memory configured to store first data comprising secrets; a processor configured to execute software, the software configured to execute instructions to read a secret from the first memory and supply the secret to the circuit; a second memory whose data is inaccessible to the software; and an interconnect coupled to the first memory, the second memory, the processor, and the circuit, the interconnect configured to receive the programmatic data transfer requests from the processor, read the secret from the first memory, write the secret to the second memory, read the secret from the second memory, and supply the secret to the circuit.

An example integrated circuit (IC) assembly can include a first electrical integrated circuit (EIC) electrically and mechanically coupled to a substrate and including a first and a second die-to-die interface circuit. The IC assembly can include a first optical transceiver engine electrically and mechanically coupled to the substrate and including a third and a fourth die-to-die interface circuit. The IC assembly can include a second optical transceiver engine electrically and mechanically coupled to the substrate and including a fifth and a sixth die-to-die interface circuit. The third die-to-die interface circuit can be electrically coupled to the first die-to-die interface circuit by first conductors of the substrate. The fifth die-to-die interface circuit can be electrically coupled to the second die-to-die interface circuit by second conductors of the substrate. The fourth and the sixth die-to-die interface circuits can be configured as disconnected from power supplies of the first and second optical transceiver engines, respectively.

An example memory circuit includes a memory cell coupled to a first row line, a second row line, a first bit line, and a second bit line, the first bit line and the second bit line coupled to a first node of the memory cell, the memory cell configured to store a bit; and a controller including a first write driver coupled to the first bit line and a second write driver coupled to the second bit line, the first write driver configured to, during a first time interval, apply a first voltage to the first bit line in response to a first control signal and a first data signal, the second write driver configured, during the first time interval, to apply the first voltage to the second bit line in response to a second control signal and the first data signal.

The subject technology is directed to electronic circuits. In an embodiment, the subject technology provides an apparatus that includes a first comparator coupled to the input terminal and configured to compare an input signal to a first threshold and to generate a first signal in response to the input signal exceeding the first threshold. The apparatus further includes a first circuit coupled to the first comparator. The first circuit is configured to initiate a first interval in response to the first signal. A second comparator is configured to generate a second signal based on a comparison between the input signal and the second threshold. The first circuit is configured to adjust the first interval based on the second signal. By adaptively adjusting the control timing based on signal conditions, the apparatus enables improved switching performance and reduced conduction losses in power control applications. There are other embodiments as well.

A device includes a transmitter and one or more processors. The one or more processors may be configured to transmit, via the transmitter, a first frame initiating a transmit opportunity (TXOP) and instructing one or more devices receiving the first frame to switch from a first mode to a second mode, determine a duration to allow the one or more devices to switch from the second mode to the first mode, generate a second frame to indicate an end of the TXOP to the one or more devices, the second frame having padding based at least on the duration, and transmit, via the transmitter, the second frame.

The disclosure describes systems and methods for improving round-trip time (RTT) measurement in wireless communication networks. An initiating station (ISTA) can transmit a null data packet announcement (NDPA) frame to a responding station (RSTA) for a first burst, causing the RSTA to skip transmitting a location measurement report (LMR) frame for that burst. The ISTA can transmit an initiator-to-responder (I2R) NDP frame to the RSTA and receive a responder-to-initiator (R2I) NDP frame from the RSTA after the first burst. The RSTA can generate the LMR frame for a second burst in response to the R2I NDP frame. For a last burst, the ISTA can transmit the NDPA frame to the RSTA, causing the RSTA to skip exchanging I2R and R2I NDP frames between the ISTA and the RSTA. The ISTA can receive the LMR frame from the RSTA during the last burst and determine the RTT.

A communication device is configured to operate as a transmitter or a receiver. As a receiver, the communication device detects data frames that failed transmission. The device can determine whether the issue that caused the failure was internal (e.g., a buffer overrun, etc.) or external (e.g., channel interference, etc.). The device communicates, to the transmitter of the data, an indication of whether the issue of the failure was internal to a receiver, for example, in a block acknowledgement frame. As a transmitter, the device can respond to the indication. If the issue was not internal, the device may correct for external causes, for example, by increasing transmission power. If the issue was internal, the device may perform no action (e.g., expecting the error to clear) or the device may perform a mitigating action such as transmitting smaller data frames, smaller aggregations of data frames, or decreasing the transmission rate.

One or more embodiments provide a method for manufacturing a semiconductor device. The method includes preparing a wafer having a first surface coupled to a carrier wafer and a second surface opposite the first surface, and mounting a semiconductor chip stack on the second surface of the wafer. The mounting is performed such that an optical interface of the semiconductor chip stack is above a peripheral region on the second surface of the wafer. The method further includes forming a photoresist pattern to cover a peripheral region of the second surface and a region of the semiconductor chip stack that includes the optical interface, forming a mold in a space surrounded by the photoresist pattern, grinding the mold such that the semiconductor chip package is exposed, removing the photoresist pattern after grinding the second, and removing the carrier wafer from the first surface of the wafer.

In an example, an analog-to-digital converter (ADC) includes a comparator having a first input, a second input, and an output, the comparator configured to compare the first input and the second input to generate the output; a first digital-to-analog converter (DAC) coupled to the first input of the comparator, the first DAC including a first plurality of unsplit capacitors and at least one first split capacitor; a second DAC coupled to the second input of the comparator, the second DAC including a second plurality of unsplit capacitors and at least one second split capacitor; first switches coupled to the first DAC; second switches coupled to the second DAC; and a first circuit configured to, in response to the output of the comparator, generate control signals for the first and second switches.

An apparatus including first and second samplers, first and second analog-to-digital converters, and a clock generator. The first sampler produces a first stream of sampled values in response to sampling an analog input signal on a first input channel. The first analog-to-digital converter generates a first stream of digital data. The second sampler produces a second stream of sampled values in response to sampling an analog input signal on a second input channel. The second analog-to-digital converter converts the second stream of sampled values into a second stream of digital data. The clock generator causes the first analog-to-digital converter to convert the first stream of sampled values into the first stream of digital data in response to a mode instruction designating a custom operating mode. The clock generator also causes the first analog-to-digital converter to convert the second stream of sampled values into the first stream of digital data in response to the mode instruction designating a standard operating mode.

A computer is configured to set up a remote direct memory access (RDMA) connection for an application, by performing the steps of: receiving, from the application, by an RDMA driver, a sequence of API requests for setting up the RDMA connection, the API requests including information for setting up the RDMA connection; transmitting, by the RDMA driver to a NIC of the computer, in response to a last API request in the sequence, a first hardware request for setting up the RDMA connection; and generating, by the NIC in response to the first hardware request, a queue pair based on the information for setting up the RDMA connection, and also configuring, by the NIC, the queue pair based on the information for setting up the RDMA connection, the queue pair including memory space for storing receive and send requests of the application.

Cooling assemblies that can be used with various types of integrated circuits to provide improved efficiency. An example integrated circuit includes a circuit die, a stiffener ring, a heat exchange structure, and a cover plate disposed on the heat exchange structure; and a clamp secured to the cover plate. The integrated circuit can also include a seal disposed between the cover plate and the heat exchange structure, where the seal prevents leakage of fluid that circulates through the heat exchange structure.

The subject technology is directed to semiconductor devices and fabrication methods thereof. In an embodiment, the subject technology provides an apparatus that includes a substrate comprising a first metal material and a first layer coupled to the substrate. The apparatus further includes a second layer coupled to the substrate via the first layer. The second layer comprises an organic material. The first layer includes a third layer comprising a first adhesion material configured to couple to the organic material, a fourth layer comprising a second adhesion material, and a fifth layer comprising a third adhesion material configured to couple to the first metal material. The multi-layer adhesion system enables reliable bonding between organic and metallic components, ensuring robust mechanical and electrical performance of the system. There are other embodiments as well.

A wireless device may include a transmitter and one or more processors. The processors may be configured to receive a plurality of spatial streams of encoded data corresponding to a number of spatial streams. The processors may be configured to modulate encoded bits of the encoded data to a set of modulated symbols using a number of bits per subcarrier stream (NBPSCS). The processors may be configured to determine a tone-mapping distance based at least on the number of spatial streams and the NBPSCS. The processors may be configured to map the set of modulated symbols onto a set of frequency subcarriers using the determined tone-mapping distance. The transmitter may be configured to transmit the encoded data to another wireless device using the set of frequency subcarriers.

Equal probability dynamic element matching functionality for use in various types of integrated circuits (e.g., communications circuits, etc.). The equal probability dynamic element matching functionality generally includes arranging circuit elements in a loop, and using both a pointer and a random number having a binary value to provide equal selection of circuit elements in the loop over time. The equal probability dynamic element matching functionality can be used to improve performance and durability of various types of integrated circuits.

An apparatus including a comparator and a plurality of replica current sources. The comparator outputs a control voltage onto an output line upon comparing a midpoint voltage with a feedback voltage. The control voltage indicates whether the feedback voltage is higher or lower than the midpoint voltage. Each of the replica current sources draws a supply voltage from a supply line. A replica current source enters into an inactive state in response to an enable signal being in a deactivating state. Upon entering the inactive state, the replica current source ceases drawing the control voltage from the output line.

A circuit including a first resistor (R21), a second resistor (R22), a current source (211) and a transistor (QP23). The first resistor (R21) is between a voltage rail and a drive interconnect. The drive interconnect and the voltage rail are electrically connected to the first resistor (R21). The second resistor (R22) is between the drive interconnect and ground. Ground and the drive interconnect are electrically connected to the second resistor (R22). The current source (211) is between the voltage rail and the drive interconnect. The drive interconnect and the voltage rail are electrically connected to the current source (211). The transistor (QP23) is between the drive interconnect and a sink interconnect. The drive interconnect and the sink interconnect are electrically connected to the transistor (QP23).

The disclosure describes systems and methods for implementing network slicing in optical access networks. The system can identify a plurality of allocation identifiers corresponding to a plurality of optical network units in a passive optical network. Each of the plurality of allocation identifiers can have one or more properties. The system can establish one or more slices, where each of the one or more slices can include a set of allocation identifiers of one or more flows having a common property of the one or more properties. The system can allocate a portion of bandwidth to each of the one or more slices. The system can associate the one or more slices with one or more virtual network operators.

A digital pre-distortion circuit and technique for a signal being amplified. Digital pre-distortion is performed using a model-based pre-distortion function. Pre-distortion is further corrected using a data-driven pre-distortion function. The model-based pre-distortion function and the data-driven pre-distortion function are trained using training data including a digital loopback signal generated by sampling a loopback signal of an amplifier, the digital pre-distorted signal input to the amplifier for a time period, and an intermediate signal output from the model-based pre-distortion function driven by the digital loopback signal or an output of the data-driven pre-distortion function. Parameters may be continually updated in order to account for changes in characteristics of the amplifier.

Compact mechanisms for attaching co-packaged devices to integrated circuit (IC) packages. An example integrated circuit includes a substrate having an outer periphery; a circuit die disposed on the substrate and contained within the outer periphery; a stiffener structure that is disposed on the substrate, contained within the outer periphery, and including a threaded opening; a compression structure secured to the stiffener structure via the threaded opening; and a co-packaged device (CPD) disposed on the substrate such that a first surface portion of the CPD contacts the compression structure and such that a second surface portion of the CPD contacts the substrate.

An assembly including a capacitive height sensor and a conditioning circuit. The capacitive height sensor detects capacitance between a read/write head and a disk surface to monitor variances in a flying height. To bring about a measurement voltage between the capacitive height sensor and the disk surface, the conditioning circuit supplies a drive current to the capacitive height sensor. The conditioning circuit ceases flowing the drive current to the capacitive height sensor upon detecting that the measurement voltage is greater than a high threshold, and commences flowing the drive current to the capacitive height sensor upon detecting that the measurement voltage is less than a low threshold.

The subject technology is directed to clock calibration systems and methods. In an embodiment, the subject technology provides an apparatus for clock calibration to minimize timing discrepancies between even and odd clock edges. The apparatus includes a first data path configured to generate a first signal, the first signal comprising a first edge and a second edge associated with even and odd clock cycles, respectively. A calibration circuit is coupled to the first data path and configured to determine a timing difference between the first edge and the second edge to calculate even-odd jitter (EOJ). This configuration enables precise calibration to reduce EOJ and ensure accurate synchronization of clock signals in high-speed communication systems.

The systems and methods for providing interference mitigation for a multiband wireless communication system are disclosed. A device can include wireless transceivers operating on different bands and a circuitry to receive a first signal via a first band and transmit a second signal via a second band. The second signal can cause an interference with the first signal. The interference can include a central portion and a tail portion. A filter can reduce, from a sample of the second signal, the central portion of the interference to provide a filtered sample signal, whose carrier frequency can be adjusted to a different carrier frequency or baseband to provide a converted sample signal. An equalizer can identify, from the converted sample signal, the tail portion of the interference to provide a third signal, which a demodulator can use to reduce the interference from the first signal.

A terminal including a transceiver, an analog-to-digital converter and control circuitry. The transceiver receives a stream of bursts from a plurality of units. One of the units is an electronic device. The analog-to-digital converter receives an upstream burst from the transceiver during an active time slot. The upstream burst is one of the bursts. In response to sampling the upstream burst at a sample rate, the analog-to-digital converter converts the upstream burst from an analog waveform into a sequence of digital values. In response to a coefficient for the electronic device being a default coefficient, the control circuitry stores the digital values into memory during the active time slot.

Method and system for direct memory access. According to an embodiment, the subject technology provides a system for facilitating memory address translation in a virtualized computing environment to enable efficient access to a graphics processing unit (GPU) by a virtual machine. The system includes a host machine equipped with a host tool configured to obtain and map address translations between a first memory address associated with the virtual machine and a second memory address associated with GPU memory. The host tool provides a mapping table containing these address mappings. A communication link is configured to transfer the mapping table from the host machine to the virtual machine. Within the virtual machine, a driver for a network communication device receives the mapping table and provides the second memory address to another address mapping table on the network communication device.

A method for improving wafer-level optical characteristic uniformity. The method includes forming a first layer of dielectric overlying the first wafer and a second layer of dielectric overlying the second wafer. The method also includes measuring a refractive index distribution of the second layer and measuring a first thickness distribution of the first layer. The method also includes determining a second thickness distribution for the first layer based on the refractive index distribution and the first thickness distribution. The method further includes removing material nonuniformly and selectively from the first layer based on the second thickness distribution, resulting in a third layer in the second thickness distribution characterized by a spectral response with a characteristic wavelength uniformity better than +/- 2.5 nm across the first wafer.

Methods and systems for adjusting phase lock loop devices. In a specific embodiment, the subject technology provides a system that includes a sampler for generating samples from a first data stream and a clock and data recovery (CDR) circuit to determine phase offset and generate a first control code. The system also includes a phase interpolator produces a first clock signal based on the first control code and a second clock signal. The system includes a first filter configured to track the phase interpolator movement, and it generates a second control code that includes a fractional divider value. The system includes a phase-locked loop (PLL) circuit that uses a reference clock to generate the second clock signal based on the third clock signal and the second control code. There are other embodiments as well.

An optical receiver unit (110) is described, the unit comprising: an anode terminal (PDA) configured to be connected to an anode of a photodiode, a cathode terminal (PDK) configured to be connected to a cathode of the photodiode, a transimpedance amplifier (TIA) having an input and an output, a first electrically conductive structure (112) coupling the anode terminal to the input, and a second electrically conductive structure (114) coupling the cathode terminal to a bias voltage supply (LDO), the second electrically conductive structure comprising two conductive lines (1141, 1142) extending on opposite sides of the first electrically conductive structure. Furthermore, an optical receiver module comprising a plurality of such units and a method of manufacturing the units are described.