Avago Technologies International Sales Patente

The subject technology is directed to an apparatus for managing data packets in a network. In an embodiment, the apparatus comprises a first memory configured to store a plurality of packets. The apparatus further comprises a queue manager configured to receive a plurality of packet descriptors and generate an aggregated packet descriptor based on the plurality of packet descriptors. The apparatus further comprises a traffic manager coupled to the queue manager. The traffic manager is configured to determine a transmission order for the plurality of packets based on the aggregated packet descriptor. A transmitter is coupled to the traffic manager and configured to transmit the plurality of packets based on the determined transmission order. This configuration enables efficient packet storage, aggregation, and transmission scheduling, optimizing overall network performance and resource utilization. There are other embodiments as well.

The subject technology is directed to a semiconductor device and methods for its fabrication and use. In an embodiment, the subject technology provides a semiconductor device that comprises a substrate having a first side and a second side. The second side comprises a cavity. A first circuit is coupled to the first side of the substrate and is characterized by a first thickness. A second circuit, comprising an RF component, is positioned within the cavity on the second side of the substrate and is characterized by a second thickness greater than the first thickness. The cavity is characterized by a first depth less than or equal to the second thickness. This configuration allows the RF component to be embedded within the substrate, optimizing the device's height and improving space utilization for compact electronic devices. There are other embodiments as well.

An example integrated circuit (IC) includes a semiconductor substrate having a first well and a second well; a first resistor disposed on the semiconductor substrate over the first well within a boundary thereof; a second resistor disposed on the semiconductor substrate over the second well within a boundary thereof, the boundary of the second well disjoint from the boundary of the first well; and a first contact to bias the semiconductor substrate at a first voltage, a second contact to bias the first well at a second voltage, and a third contact to bias the second well at a third voltage.

The present invention is directed to electrical circuits. According to a specific embodiment, the present invention provides a device that includes a clock generator configured to generate a first clock signal and a second clock signal, with the second clock signal locked to the first clock signal. The device further includes an input path configured to carry an input signal, an injection circuit configured to provide the second clock signal into the input path during calibration, and a plurality of delay elements configured to generate a plurality of delayed signals using the first clock signal. There are other embodiments as well.

A wireless device supports roaming to a second access point if signal strength falls below a threshold or a connection is disrupted. The wireless device generates nonce values used for encryption and/or to protect against a replay attack. The nonce values a generated according to rules designed to minimize nonce reuse after roaming within a mobility domain. The wireless device may also be configured to generate encryption keys with a device of the mobility domain before a connection is established. The encryption keys are used after roaming to encrypt the earliest data frames sent after the roam.

A power transceiver includes a power converter, a current regulator and a voltage regulator. The power converter converts electric power into an unregulated current in response to wirelessly receiving electric power. The current regulator modifies a system current in response to adjusting the unregulated current. The voltage regulator maintains the regulated voltage at a voltage in response to converting the system current into a regulated voltage.

In some implementations, an apparatus may include a receiver and on or more processors. The one or more processors may be configured to identify a low-density parity-check (LDPC) code corresponding to a bipartite graph comprising a set of edges connected between a first set of nodes and a second set of nodes. The one or more processors may be configured to generate a first set of messages and a second set of messages using the encoded data. The one or more processors may be configured to communicate the first set of messages with the first subset and the second set of messages with the second subset, concurrently using the bipartite graph. The one or more processors may be configured to identify decoded data based at least on processing of the first set of messages and the second set of messages.

A wireless device can include a first radio configured to transmit over a first link and a second link of a first wireless band. to a first device. The first device includes a circuit configured to provide data across a connection comprised of one or more links to a second device. The circuit is configured to detect a presence of at least a portion of a packet using a relationship of a guard tone and a signal tone in a bandwidth. The wireless device may be able to recover from blindness with less latency.

The technical solutions can enable the AP to identify that the AP communicates with a client device according to a quality of service (QoS) of the client device at a first capability mode associated with a first power level of the AP. The AP can determine that the AP is capable of communicating with the client device according to the QoS at a second capability mode associated with a second power level of the AP, the second power level lower than the first power level. The AP can transmit, responsive to the determination, a frame to notify the client device that the AP is to transition from the first capability mode to the second capability mode. The AP can communicate, subsequent to the transmission of the frame, with the client device at the second capability mode.

An example receiver includes a comparator configured to compare an analog signal and a reference signal; an analog-to-digital converter (ADC) having an input configured to receive the analog signal and an output configured to supply a digital signal; a first circuit configured to supply the analog signal to the input of the ADC, the first circuit configured to apply, under control by output of the comparator, a first operation to the analog signal; and a second circuit configured to receive the digital signal from the output of the ADC, the second circuit configured to apply, under control of the output of the comparator, a second operation to the digital signal. In some examples, the analog signal can be an orthogonal frequency division multiplexing (OFDM) signal.

An example phase interpolator in an integrated circuit (IC) includes: a first circuit including a transistor pair and a current source, the transistor pair including a first transistor coupled between a first node and the current source, and second transistor coupled between a second node and the current source, a gate of the first transistor configured to receive a first clock signal and a gate of the second transistor configured to receive a second clock signal that is antiphase with the first clock signal; a load circuit including a first inductor coupled between the first node and the second node and a resistor coupled between a voltage source and a center terminal of the first inductor; and a second circuit coupled between the center terminal of the first inductor and an alternating current (AC) ground, the second circuit tuned to conduct a second harmonic of the first clock signal.

Systems and methods transfer video data to an image processing system from a video source. Pixel data is received in a local buffer of a network interface controller and provided in a video transport packet. The video transport packet includes the pixel data, a media access control header and a video header. The video transport packet is received by another network interface controller that provides the pixel data directly into a video frame buffer of the image processing system.

A semiconductor device with a mixed channel that is suitable for operability under high operating voltages (e.g., 2.5 volts to 3.3 volts). The semiconductor device includes a drain; a source; a channel comprising a first nanosheet and a second nanosheet; sacrificial layer disposed between the first nanosheet and the second nanosheet; and a gate formed around the channel.

Audio synchronization is provided. A method includes establishing, by a primary earbud of a pair of earbuds, a first connection with a device, the primary earbud receiving audio data from the device via the first connection. The method includes establishing, between the primary earbud and a shadow earbud, a bridge connection, the shadow earbud receiving the audio data and link characteristics via the bridge connection to establish a shadow connection with the device to receive the audio data from the device. The method includes maintaining, by the shadow earbud, a timing relationship between the bridge connection and the shadow connection. The method includes detecting, by the shadow earbud, a failure to receive on the shadow connection. The method includes using, by the shadow earbud, the timing relationship to synchronize a timing window for which to communicate with the device.

An apparatus including a buck circuitry and logic circuitry. The buck circuitry charges a flying capacitor with a voltage in response to a device state being in a charging state and discharges the voltage from the flying capacitor in response to the device state being in a discharging state. The logic circuitry causes the buck circuitry to transition the device state in response to detecting voltage balance during a reference time period and causes the buck circuitry to repeat the device state occurring at the reference time period in response to detecting voltage imbalance during the reference time period.

An example network switch includes: a hardware platform; a first switch port, supported by the hardware platform, configured to receive first network traffic for a network; and switch logic, supported by the hardware platform, configured to copy the first network traffic received by the first switch port to generate mirrored traffic for a second switch port in the network, the switch logic further configured to embed metadata into the mirrored traffic, the metadata including information extrinsic to the first network traffic, the switch logic further configured to send the mirrored traffic to a device connected to the second switch port.

An amplifier includes a first transconductance circuit (204), which includes a first output coupled to a first current source (32, 34), a first input, a first network (205), and a cascode circuit (52, 54); and a second transconductance circuit (206), which includes a second output coupled to a second input and a second current source (64, 66); wherein the first current source (32,34) is coupled to a supply voltage (Vdd) and the second current source (64, 66) is coupled to an electrical ground; and wherein the first output is coupled to the second output.

The subject technology is directed to systems and methods for sensor baseline detection and compensation. In an embodiment, the subject technology provides an apparatus comprising a first amplifier configured to receive a current signal and generate a first voltage signal associated with the current signal. The apparatus also comprises a first circuit configured to generate a second voltage signal based on the first voltage signal. The first circuit further comprises a switch configured to adjust the second voltage signal in response to changes in the first voltage signal, and a control circuit configured to control the rate of adjustment of the second voltage signal. There are other embodiments as well.

In an embodiment, a semiconductor device includes a wiring substrate. A chip, such as microchip, integrated circuit device, a semiconductor die, or the like is on a first surface of the wiring substrate. A plurality of protruding portions are on a second surface of the wiring substrate. Each protruding portion includes a solder reservoir space therein that can contain or be filled with solder so as to permit solder from the reservoir space to flow outward in a solder reflow process for bonding the semiconductor device to a circuit board or the like. The solder from the reservoir is available to compensate for differences in gap distances between the semiconductor device and a circuit board or the like that arise in the manufacturing of electronic devices when attempting to bond a semiconductor device to a circuit board. The protruding portions may comprise tubes, posts, pairs of plates, or the like.

An example computing system includes a hardware platform including a central processing unit (CPU), volatile memory, storage devices, and a storage controller; software, executing on the hardware platform, the software configured to: discover, by the storage controller, the storage devices; create, by the storage controller, pools of the storage devices; obtain, by first software executing on the CPU, information describing the pools; determine, by the first software in cooperation with the storage controller, an address space for each of the pools; and communicating, from the software to the storage controller, a storage transaction referencing a first pool of the pools and a first address in the address space for the first pool.

A module including a first slice and a second slice. The first slice and the second slice receive data from a plurality of inputs. A first stage of the first slice selects a first subset of the inputs in synchronization with an edge of a first clock. In synchronization with a second clock, a second stage of the first slice selects an input from the first subset. A first stage of the second slice selects a second subset of the inputs in synchronization with an edge of the second clock. In synchronization with the first clock, a second stage of the second slice selects an input from the second subset.

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