Avago Technologies International Sales Patente

A data plane of a network switch can include: a packet switch including a first port and a second port; a first processor, coupled to the packet switch and a control plane, the first processor comprising: a first digital circuit configured to: receive a first payload of a first packet ingress to the first port; and convert first numerical data in the first payload from a first format to a second format; and a second digital circuit configured to: receive the first numerical data from the first digital circuit and second numerical data; and perform a first compute operation with the first and second numerical data as input; wherein the first processor is configured to return a second packet to the packet switch for egress from the second port, a second payload of the second packet including numerical data that results at least in part from the first compute operation.

The present disclosure provides a system for mitigating dielectric absorption in a photodiode sensing circuit. The system includes a photodetector array comprising a plurality of photodiode and a sensing circuit coupled to the photodetector array. The sensing circuit comprises a switch matrix configured to selectively route signals from the photodiode, an amplifier array comprising at least one transimpedance amplifier, a reference generator configured to apply a reference voltage to at least one photodiode, and a timing generator configured to control switching between sequence of states of the system, including a sleep state, a pre-charge state, and an active state. The system enables effective mitigation of dielectric absorption by implementing a pre-charge state before transitioning to an active sensing state.

An apparatus that includes a first stage being coupled to the input terminal to receive an input signal and configured to receive a first bias current. The apparatus further includes a second and a third stage coupled to the first stage being characterized by a first state and a second state. The first state is associated with a first power level and the second state is associated with a second power level lower than the first power level. The third stage comprises a first output and a second output, the first output being configured to provide an output signal coupled to the output terminal and the second output being coupled to the first stage. By utilizing programmable power modes and maintaining a stable bias voltage, the apparatus reduces power consumption and minimizes kickback noise by ensuring smooth switching between power levels.

Described embodiments provide systems and methods for profiling low latency applications using telemetry. A data processing system can include one or more processors and memory. The data processing system can receive telemetry data for a plurality of flows of packets. The data processing system can determine, using the telemetry data, a variance of bandwidth, a variance of packet lengths, and a variance of inter-arrival times between packets for each of the flows of packets. The data processing system can determine a type of application for a flow of the flows of packets based at least on a signature of the variance of bandwidth, the variance of packet lengths, and the variance of inter-arrival times for the flow. The data processing system can take, in response to determining the type of application, one or more actions to provide a quality of service for the flow according to the type of application.

In some implementations, a wireless device may include one or more processors. The one or more processors may be configured to perform first soft demapping using sphere decoding on first data relating to a first stream and a second stream among a plurality of spatial streams. The one or more processors may be configured to perform second soft demapping using sphere decoding on second data relating to the first stream and the second stream, different from the first data. The one or more processors may be configured to determine, using a result of the first soft decoding and a result of the second soft decoding, log likelihood ratio (LLR) values of the first stream and the second stream.

In some implementations, an apparatus may include a receiver, a plurality of circuits, and on or more processors. The plurality of circuits may include a same set of input/output (I/O) interfaces and performing a respective function of processing data at the PHY layer or the MAC layer. The one or more processors may be configured to select a first set of circuits of the plurality of circuits to use as a first datapath to process, through each of the first set of circuits, data received by the receiver. Each of the first set of circuits can be configured to communicate with another one of the first set of circuits using the same set of I/O interfaces and perform the respective function of processing the data.

In some implementations, a device may one or more processors. The one or more processors may be configured to perform soft demapping using sphere decoding in multiple input multiple output (MIMO) systems and using different modulation sizes in unequal quadrature amplitude modulation (QAM) across a plurality of spatial streams.

In an embodiment, a transistor has a semiconductor layer with a first-type region and a second-type region adjacent to the first-type region. An insulating structure extends into the second-type region. A first conductor is on the first-type region. A second conductor is on the second-type region. A first gate structure is on the semiconductor layer between the first and second conductor. The first gate structure includes semiconductive layers that are vertically spaced from each other and a first gate metal that contacts the semiconductive layers. A second gate structure is on the semiconductor layer between the first gate structure and the second conductor. The second gate structure includes semiconductive layers that are vertically spaced from each other. The second gate structure further includes a second gate metal that contacts the semiconductive layers of the second gate structure.

A computer system of a vehicle comprising a physical layer (PHY) device, is configured to perform the following steps to detect degradation in a cable: communicating with another component of the vehicle using the PHY device and the cable at a first timing; capturing first characteristics of at least one first signal communicated with the other component, and determining a first degradation parameter using the first characteristics; communicating with the other component of the vehicle using the PHY device and the cable at a second timing that is after the first timing; capturing second characteristics of at least one second signal communicated with the other component, and determining a second degradation parameter using the second characteristics; and comparing the first degradation parameter with the second degradation parameter, and generating a degradation warning if a difference between the first and second degradation parameters indicates degradation in the cable.

The subject technology is directed to electronic circuits. In an embodiment, the subject technology provides an apparatus that includes an input terminal configured to receive an input signal. The apparatus further includes a first circuit coupled to the input terminal, the first circuit comprising a first transistor coupled to the input terminal and a level-shifter coupled to the first transistor. A second circuit is coupled to the first circuit, the second circuit comprising a second transistor, the second transistor including a base terminal coupled to a first supply voltage. The apparatus further includes an amplifier comprising a first input and an output, the amplifier being configured to generate an output signal by amplifying the input signal. By optimizing electrostatic discharge (ESD) protection, electrical overstress (EOS) protection, and leakage control in the analog front-end (AFE), the apparatus reduces leakage current and minimizes nonlinearity. There are other embodiments as well.

An example memory circuit can include: a memory cell coupled to a first word line, a second word line, a first bit line, and a second bit line, the first word line selectively coupling the memory cell to the first bit line, the second word line selectively coupling the memory cell to the second bit line; a first sense amplifier coupled to the first bit line and a reference voltage, the first sense amplifier configured to compare voltage of the first bit line to the reference voltage; and a second sense amplifier coupled to the second bit line and the reference voltage, the second sense amplifier configured to compare voltage of the second bit line to the reference voltage.

A vehicle alert response system of a vehicle is configured to handle an alert to identify a vehicle of interest, by performing the steps of: detecting the alert using a communication interface, the alert including a target license plate number of the vehicle of interest; capturing, using a video camera, video data showing a captured license plate number; identifying the captured license plate number by performing optical character recognition (OCR) to extract characters of the captured license plate number from pixels of the video data and decode the extracted characters; comparing the target license plate number to the captured license plate number to determine that the target license plate number matches the captured license plate number; and transmitting, using the communication interface, a response to the alert including the location information and indicating that the target license plate number has been identified from the video data.

An integrated circuit (IC) may be configured to receive and process input signals with respect to a first ground that is coupled to a second ground. The input signals may be referenced to the second ground. The IC may be configured to receive, by the first input terminal and by a second input terminal of the IC that is coupled to the second ground, noise signals. The IC may be configured to route the input signals and the noise signals from the first input terminal to a first differential input terminal of a differential signal converter of the IC and the noise signals from the second input terminal to a second differential input terminal of the differential signal converter while maintaining symmetry between an input impedance toward the first differential input terminal and an input impedance toward the second differential input terminal.

An example switching regulator includes: a first switch including a first terminal coupled to a first node, a second terminal coupled to a second node, and a third terminal coupled to a third node, the first node configured to supply a first voltage, the second node configured to supply an electrical ground; a first network coupled between the third node and the second node, the first network including a fourth node configured to supply a second voltage; a comparator having an input configured to receive a third voltage and a fourth voltage and an output coupled to control the first switch, the fourth voltage being proportional to the second voltage; and a digital circuit coupled to the comparator and the third node, the digital circuit configured to: measure a frequency of a fifth voltage at the third node; and adjust a hysteresis range of the comparator based on the frequency.

An apparatus for analog-to-digital conversion comprising a first module with a comparator and digital-to-analog converters, and a second module with an amplifier. The apparatus implements input chopping by connecting capacitors to differential inputs through switches, and output chopping via an output chopper. Dynamic refresh is achieved using a switch to periodically connect differential inputs to a voltage reference. The apparatus further incorporates digital common-mode rejection ratio (CMRR) enhancement by processing signals from pseudo-differential first stage analog-to-digital converters.

A device is provided herein. The device includes a signal input, an operational amplifier (op-amp) comprising a non-inverting op-amp input, an inverting op-amp input, and an op-amp output, a summer coupled to the op-amp output, a second summer input coupled to the signal input, and a summer output, and a low-pass filter comprising a low-pass filter input coupled to the summer output and a low-pass filter output coupled to the inverting op-amp input. The device processes electrophysiology signals by combining feedforward and feedback paths to achieve DC offset and low-frequency interference rejection while maintaining high input impedance and signal amplification.

A device may include a signal input, an operational amplifier (op-amp) comprising a noninverting op-amp input coupled to the signal input, an inverting op-amp input, and an op-amp output, a capacitor comprising a plurality of ports and a switched capacitor arrangement. The switched capacitor arrangement includes a first switch coupled between a first capacitor port and the inverting op-amp input, a second switch coupled between a second capacitor port and the op-amp output, a third switch coupled between a third capacitor port and the signal input, and a fourth switch coupled between a fourth capacitor port and ground. The device may process electrophysiology signals by implementing switched-capacitor dual-path DC cancellation to achieve offset and low-frequency interference rejection while maintaining high input impedance and signal amplification.

The technical solutions are directed to MAC address protection for frame integrity verification. A sender device can compute, using a temporal key, TK, programmed in hardware, a first key for a body (232) of a frame (230) and a second key for a header (234) of the frame (230), different from the first key. The sender can encrypt the body (232) of the frame (230) at a machine access control, MAC, layer using the first key and the header (234) of the frame (230) at the MAC layer using the second key. The sender can compute a first MIC of the encrypted frame (230) using the first key and a second MIC of a content of the header (234) at the MAC layer using the second key. The sender can transmit the frame (230) with the first MIC and the second MIC to a receiver (204) configured to determine integrity of the header (234) of the frame (230) based on the second MIC.

The subject technology is directed to semiconductor devices and fabrication methods thereof. In an embodiment, the subject technology provides an apparatus that includes a functional die coupled to a first side of a substrate and a second die coupled to a second side of the substrate opposite the first side. The second die is at least one of (1) about a same thickness as the first die, (2) about a same area as the first die, (3) in about a same location as the first die, or (4) formed from a similar material as the first die. Providing the second die on the second side of the substrate counterbalances the thermomechanical stresses or forces produced by the first die. Thus, reducing the stresses on the substrate than can cause misalignment between semiconductor components or electrical failures. There are other embodiments as well.

The subject technology is directed to electronic circuits. In an embodiment, the subject technology provides an apparatus that includes a resistor unit comprising a first transistor and a second transistor. The first transistor includes a first terminal and the second transistor includes a second terminal. The first terminal is coupled to the second terminal. The resistor unit is configured to provide a first resistance between the first terminal and the second terminal. The apparatus further includes a reset unit coupled to the resistor unit and configured to provide a second resistance between the first terminal and the second terminal in response to a control signal. The second resistance is lower than the first resistance. The subject technology provides a reset mechanism that enables fast recovery from high-resistance states, ensuring precise resistance control and improved performance in high-impedance applications.

Systems and methods for multi-link power management indication using base-3 compression are disclosed. A multi-link station can include a communication interface and a processor configured to communicate with an access point using a plurality of links. The processor can identify a ternary state of power management for each link of the plurality of links, determine a change in power management state of one or more links, generate, using a ternary encoding, a value for a power management field to identify the change in power management state of the one or more links, and communicate, via the communication interface, a frame comprising the power management field via one link of the plurality of links to the access point. The disclosed techniques enable efficient signaling of power management state transitions for multiple links within a constrained bit field, reducing signaling overhead and supporting scalable multi-link wireless communication.

An example computing system includes: a compute node having a central processing unit, CPU, (12) and a memory (14); a first device (20) connected to the compute node through a peripheral interconnect; a switch (16) of the peripheral interconnect having a first port (225U) coupled to the CPU (12) and a second port (225D1) coupled to the first device (20); and a controller (22) coupled to the switch (16) via an out-of-band interconnect (227) with respect to the peripheral interconnect; the controller (22) configured to send a request to monitor the peripheral interconnect to the switch (16) and to read results of monitoring from the switch (16); and the switch (16) configured to monitor the peripheral interconnect in response to the request and store the results of the monitoring.

An electronic device includes a network interface configured to communicate data signals via channels on a network, computer-readable storage media storing sequences of instructions, and processing circuitry configured to execute the sequences of instructions to perform operations. The operations may include sampling the data signals communicated via the network interface, determining attributes of the channels based on a first set of data signal samples, normalizing a second set of data signal samples based on the determined attributes of the channels, processing the normalized second set of data signal samples using a machine learning model to generate an indication of impairment in the channels, determining, based on the indication, characteristics of the impairment in the channels, and generating and transmitting a notification comprising the determined characteristics of the impairment to a controller via the network interface.

The subject technology is directed to signal processing systems and methods. In an embodiment, the subject technology provides an apparatus that includes an input terminal configured to receive an input signal and a converter coupled to the input terminal. The converter is configured to generate a first signal based at least on the input signal. The apparatus further includes an amplifier coupled to the converter, the amplifier being configured to generate a second signal by amplifying the first signal. A first switching element is coupled to the converter and the amplifier and is configured to perform chopping by modulating the first signal, converting a first component of the second signal to a first chopping frequency higher than the first frequency. By applying chopping techniques, the apparatus effectively mitigates low-frequency noise, enhancing the accuracy and performance of signal processing operations. There are other embodiments as well.

An electronic device is configured to filter sample data on the electronic device from data sources according to a sample filter configuration, where the data sources operate at respective functional layers, and to generate feature data from the sample data according to a feature generator configuration. The generated feature data is aggregated into queues in input formats corresponding to machine learning models activated according to a context switch policy, and inference operations are executed by providing feature data from the queues as input data to the machine learning models to generate output data. The status of the electronic device may be determined based on the generated output data, and the sample filter configuration, the feature generator configuration, or the context switch policy may be adapted based on the determined status of the electronic device to modify subsequent iterations of the filtering, generating, aggregating, or executing operations.

The disclosure describes systems and methods for efficient power and bandwidth utilization during Bluetooth low energy active scans between scanners and advertisers. A scanner, via a Bluetooth controller coupled with a host processor, can identify attributes of advertisers based on advertisement packets received via Bluetooth. The scanner can store the attributes for each advertiser in a data structure. Upon receiving an advertisement packet from an advertiser, the scanner can search the stored attributes and determine a score for the advertiser. Based on the score, the scanner can determine whether to suppress the transmission of a scan request, transmit the scan request at a specific priority, or adjust transmit power of the scan request.

The disclosure describes systems and methods for periodic monitoring of network latency. A client device can receive, from each node of a plurality of nodes between the client device and a device providing access to an internet service provider, a packet identifier and a timestamp for each data packet selected by each node. The client device can identify, for each packet identifier received, a second timestamp of receipt by the client device of each data packet corresponding to each packet identifier. The client device can determine, based at least on timestamps associated with one or more packet identifiers received from each corresponding node and second timestamps for the packet identifiers, a respective latency between the client device and the corresponding node.

Amplifier circuits that can provide improved performance by mitigating the effects of dielectric absorption. An example integrated circuit includes a first pin connectable to a photodiode to receive an input current from the photodiode; a second pin connectable to a capacitor; an amplifier comprising an inverting input terminal and an output terminal; a guard buffer connected between the second pin and the inverting input terminal of the amplifier; and a third pin connected to the output terminal of the amplifier to provide an output voltage indicative of the input current.

Amplifier circuit that can provide improvements in terms of performance and power efficiency. An example integrated circuit includes a first pin connectable to a photodiode to receive an input current from the photodiode; an amplifier connected to the first pin; a second pin connected to the amplifier to provide an output voltage indicative of the input current from the photodiode; a current source circuit connected between the first pin and the second pin; an analog-to-digital converter (ADC) circuit connected between the second pin and the current source circuit; and a controller configured to, during a first time period, measure a first current associated with the photodiode using the ADC circuit and, during a second time period, cause the current source circuit to provide a second current to the amplifier to cancel the first current.

The subject technology is directed to electronic circuits. In an embodiment, the subject technology provides an apparatus that includes an input terminal configured to receive an input clock signal. The apparatus further includes a delay controller coupled to the input terminal and configured to generate a first clock signal by providing a first delay to the input clock signal. An accumulator is coupled to the delay controller and configured to generate a first signal and adjust the first delay based on a second signal, the second signal being associated with an in-rush current threshold. A first circuit is coupled to the input terminal and configured to generate an output clock signal based at least on the first clock signal. By implementing a closed-loop control mechanism, the apparatus adjusts the duty cycle based on real-time current feedback, ensuring stable power-up operation without excessive delays. There are other embodiments as well.

Methods, systems, and devices for synchronizing Bluetooth access grants in Wi-Fi-connected devices are described. In some implementations, a method may include establishing a Wi-Fi connection between a first device and a second device, both equipped with Bluetooth capabilities. The method may involve determining a target beacon transmit time for the Wi-Fi connection and synchronizing Bluetooth access grants between the first and second devices based on the target beacon transmit time. Consequently, medium access may be granted to Bluetooth on both the first and second devices simultaneously in response to the synchronized Bluetooth access grants, thereby enhancing the efficiency of medium usage and improving overall device coexistence and performance in Wi-Fi/Bluetooth combination environments.

The disclosure describes systems and methods for establishing a constant bit rate data pipe between access points and stations. An access point can receive, from a station, a request indicating a bandwidth for a low latency application running on the station. Responsive to acceptance of the request by the access point, the station can withhold transmissions of a request-to-send (RTS) frame to the access point. The access point can determine, based at least on the bandwidth of the request, a frequency by which to send a clear-to-send (CTS) frame to the station. The access point can transmit the CTS frame to the station according to the determined frequency.

In an embodiment, a packaged integrated circuit device includes a package substrate. The package substrate may be flip-chip type package substrate. A layer is disposed on the package substrate. An interposer is disposed on the layer. This layer may have passthrough type through vias permitting electrical interconnections between the package substrate and the interposer. The interposer may have various wiring layers and circuit components therein. One or more dies are disposed on the interposer. A die may be an application specific integrated circuit devices, a high-speed memory device, or the like. The layer has a coefficient of thermal expansion that is between a coefficient of thermal expansion of the interposer and a coefficient of thermal expansion of the package substrate. The layer can function to intermediate stresses or strains arising during manufacturing and/or operation related to thermal expansion differences in components.

The subject technology is directed to signal processing systems and methods. In an embodiment, the subject technology provides an apparatus that includes a first input terminal and a second input terminal configured to receive respective input signals. A first converter and a second converter generate corresponding output signals based on the input signals. A first circuit, coupled to both converters, determines a gain mismatch between them based on their output signals and adjusts at least one of the signals to compensate for the mismatch. By compensating for gain mismatch in the digital domain, the apparatus improves the common-mode rejection ratio (CMRR) and enhances the accuracy and reliability of analog-to-digital conversion. There are other embodiments as well.

An access point (AP) point in a wireless local area network (WLAN) may include circuitry configured to transmit, to a station (STA) in the WLAN, a beacon including a beacon payload. A first set of information elements associated with the access point may be advertised within the beacon payload. The beacon payload may include an indicator indicating that the AP is associated with a second set of information elements that is not advertised in the beacon payload. The STA may include circuitry configured to transmit, to the AP, a request for the second set of information elements. The STA may receive, from the AP and in response to the request, a response including an indication of the second set of information elements.

A station (STA) may connect to an access point (AP) via a plurality of wireless links. The STA may determine to transition a power management state of at least a first wireless link, of the plurality of wireless links, to a transitioned state. The STA may transmit, to the AP and over an available wireless link of the plurality of wireless links, a frame including protected data indicating the transitioned state of the first wireless link. The AP may transition the first wireless link to the transitioned state.

A user device is configured to provide device assistance to a user of the user device, by performing the steps of: detecting a query provided by the user, the query prompting the user device for help resolving an issue; generating user manual context using a retrieval-augmented generation (RAG) neural network; identifying, from state information about the user device, a subset of the state information that is associated with the query; generating device assistance information for the issue using a local language neural network, the device assistance information containing at least one of: (1) identification of a system action for the user device to perform and (2) a message for the user; in response to the device assistance information identifying the system action, executing the system action at the user device; and in response to the device assistance information containing the message, outputting the message from the user device.

Methods, systems, and devices for exchanging subband puncture information for network throughput management are described. In some examples, an access point may receive an action frame from a station device, which includes a disabled subchannel bitmap subfield that indicates subband puncturing information based on localized interference detected by the station device. The access point may then determine a negotiated subband puncturing pattern that considers both the station device's and the access point's detected subband puncturing information. Subsequently, the access point may transmit an action frame back to the station device containing this negotiated subband puncturing pattern. Both the access point and the station device may adhere to this negotiated subband puncturing pattern for future unicast frame exchanges, thereby enhancing network efficiency by effectively managing packet transmissions and reducing packet collisions.

An access point (AP) may establish multiple virtual networks in a wireless local area network (WLAN) that are associated with a basic service set identifier (BSSID) of the AP and unique service set identifiers (SSIDs). The AP may transmit, to a station (STA) in the WLAN, a beacon including beacon data indicating the BSSID and at least one of an SSID that is not associated with the multiple virtual networks or an indicator that the AP is associated with one or more virtual networks. The STA may determine, based on the BSSID, to connect to a virtual network of the multiple virtual networks. The STA may transmit, to the AP, a request for discovery of the virtual network indicating a unique SSID of the virtual network. The STA may receive, from the AP and based on the request, a response confirming that the virtual network is available.

A mixed-signal unit including a sampler circuit and a tracking filter. The sampler circuit converts a code into a reference signal. In response to comparing an input signal to the reference signal, the sampler circuit produces a bitstream. Upon receiving the bitstream from the sampler circuit, the tracking filter updates the code using information contained in the bitstream. The tracking filter outputs the code to the sampler circuit in response to the tracking filter updating the code.