Avago Technologies International Sales

A data plane of a network switch can include: a packet switch including a first port and a second port; a first processor, coupled to the packet switch and a control plane, the first processor comprising: a first digital circuit configured to: receive a first payload of a first packet ingress to the first port; and convert first numerical data in the first payload from a first format to a second format; and a second digital circuit configured to: receive the first numerical data from the first digital circuit and second numerical data; and perform a first compute operation with the first and second numerical data as input; wherein the first processor is configured to return a second packet to the packet switch for egress from the second port, a second payload of the second packet including numerical data that results at least in part from the first compute operation.

The present disclosure provides a system for mitigating dielectric absorption in a photodiode sensing circuit. The system includes a photodetector array comprising a plurality of photodiode and a sensing circuit coupled to the photodetector array. The sensing circuit comprises a switch matrix configured to selectively route signals from the photodiode, an amplifier array comprising at least one transimpedance amplifier, a reference generator configured to apply a reference voltage to at least one photodiode, and a timing generator configured to control switching between sequence of states of the system, including a sleep state, a pre-charge state, and an active state. The system enables effective mitigation of dielectric absorption by implementing a pre-charge state before transitioning to an active sensing state.

An apparatus that includes a first stage being coupled to the input terminal to receive an input signal and configured to receive a first bias current. The apparatus further includes a second and a third stage coupled to the first stage being characterized by a first state and a second state. The first state is associated with a first power level and the second state is associated with a second power level lower than the first power level. The third stage comprises a first output and a second output, the first output being configured to provide an output signal coupled to the output terminal and the second output being coupled to the first stage. By utilizing programmable power modes and maintaining a stable bias voltage, the apparatus reduces power consumption and minimizes kickback noise by ensuring smooth switching between power levels.

Described embodiments provide systems and methods for profiling low latency applications using telemetry. A data processing system can include one or more processors and memory. The data processing system can receive telemetry data for a plurality of flows of packets. The data processing system can determine, using the telemetry data, a variance of bandwidth, a variance of packet lengths, and a variance of inter-arrival times between packets for each of the flows of packets. The data processing system can determine a type of application for a flow of the flows of packets based at least on a signature of the variance of bandwidth, the variance of packet lengths, and the variance of inter-arrival times for the flow. The data processing system can take, in response to determining the type of application, one or more actions to provide a quality of service for the flow according to the type of application.

A computer system of a vehicle comprising a physical layer (PHY) device, is configured to perform the following steps to detect degradation in a cable: communicating with another component of the vehicle using the PHY device and the cable at a first timing; capturing first characteristics of at least one first signal communicated with the other component, and determining a first degradation parameter using the first characteristics; communicating with the other component of the vehicle using the PHY device and the cable at a second timing that is after the first timing; capturing second characteristics of at least one second signal communicated with the other component, and determining a second degradation parameter using the second characteristics; and comparing the first degradation parameter with the second degradation parameter, and generating a degradation warning if a difference between the first and second degradation parameters indicates degradation in the cable.

In an embodiment, a transistor has a semiconductor layer with a first-type region and a second-type region adjacent to the first-type region. An insulating structure extends into the second-type region. A first conductor is on the first-type region. A second conductor is on the second-type region. A first gate structure is on the semiconductor layer between the first and second conductor. The first gate structure includes semiconductive layers that are vertically spaced from each other and a first gate metal that contacts the semiconductive layers. A second gate structure is on the semiconductor layer between the first gate structure and the second conductor. The second gate structure includes semiconductive layers that are vertically spaced from each other. The second gate structure further includes a second gate metal that contacts the semiconductive layers of the second gate structure.

In some implementations, a device may one or more processors. The one or more processors may be configured to perform soft demapping using sphere decoding in multiple input multiple output (MIMO) systems and using different modulation sizes in unequal quadrature amplitude modulation (QAM) across a plurality of spatial streams.

In some implementations, a wireless device may include one or more processors. The one or more processors may be configured to perform first soft demapping using sphere decoding on first data relating to a first stream and a second stream among a plurality of spatial streams. The one or more processors may be configured to perform second soft demapping using sphere decoding on second data relating to the first stream and the second stream, different from the first data. The one or more processors may be configured to determine, using a result of the first soft decoding and a result of the second soft decoding, log likelihood ratio (LLR) values of the first stream and the second stream.

In some implementations, an apparatus may include a receiver, a plurality of circuits, and on or more processors. The plurality of circuits may include a same set of input/output (I/O) interfaces and performing a respective function of processing data at the PHY layer or the MAC layer. The one or more processors may be configured to select a first set of circuits of the plurality of circuits to use as a first datapath to process, through each of the first set of circuits, data received by the receiver. Each of the first set of circuits can be configured to communicate with another one of the first set of circuits using the same set of I/O interfaces and perform the respective function of processing the data.

An integrated circuit (IC) may be configured to receive and process input signals with respect to a first ground that is coupled to a second ground. The input signals may be referenced to the second ground. The IC may be configured to receive, by the first input terminal and by a second input terminal of the IC that is coupled to the second ground, noise signals. The IC may be configured to route the input signals and the noise signals from the first input terminal to a first differential input terminal of a differential signal converter of the IC and the noise signals from the second input terminal to a second differential input terminal of the differential signal converter while maintaining symmetry between an input impedance toward the first differential input terminal and an input impedance toward the second differential input terminal.