NXP Semiconductors Patente

Aspects of the disclosure are directed to allocating bandwidth. As may be implemented in accordance with one or more embodiments, respective amounts of bandwidth are allocated to respective application groups for each memory access cycle in a set of memory access cycles. Initial bonus bandwidth is provided to a first one of the application groups during one of the memory access cycles. The bonus bandwidth may include at least a portion of bandwidth allocated to and unused by one of the other respective application groups during the memory access cycle. Additional bonus bandwidth is selectively provided to the first application group during one of the memory access cycles based on the initial bonus bandwidth and a maximum amount of bonus bandwidth defined for the set of memory access cycles, in response to bandwidth allocated to one of the other respective application groups during the subsequent memory access cycle being unused.

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In accordance with an aspect of the present disclosure, a communication system is provided, comprising: a first ultra-wideband (UWB) transmitter configured to be coupled to a first antenna; a second UWB transmitter configured to be coupled to a second antenna; a controller configured to cause the first UWB transmitter to transmit a first packet to an external communication device, wherein the first packet contains a predefined code; wherein the controller is further configured to cause the second UWB transmitter to transmit a second packet to the external communication device, wherein the second packet contains a cyclically shifted version of said predefined code. In accordance with another aspect of the present disclosure, a communication device is provided, comprising: an ultra-wideband (UWB) receiver configured to be coupled to an antenna, wherein the UWB receiver is further configured to receive at least a first packet and a second packet from an external communication system, wherein the first packet contains a predefined code and the second packet contains a cyclically shifted version of said predefined code; a processing unit configured to correlate the first packet and the second packet received by the UWB receiver with the predefined code. In accordance with further aspects, corresponding methods of operation are conceived, as well as computer programs for carrying out said methods.

A method of dynamic configuration of reaction policies in virtualized fault management system includes disabling a fault handler circuit comprising a reaction core in response to receiving a request to modify a respective first reaction policy including a plurality of first recovery actions of the reaction core, wherein each of the first recovery actions is responsive to a respective fault indication. At least one event status is cleared from an event table of the fault handler circuit. The at least one event status is set in response to the fault handler circuit receiving the respective fault indication. The reaction core is configured with a second reaction policy including a plurality of second recovery actions.

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A method, system, apparatus, and architecture are provided for validating one or more sensors by collecting and processing sensor data signals from on-board vehicle sensors to generate a local environmental map identifying one or more first traffic features located in an exterior environment of the vehicle, by collecting and processing sensor data signals from a remote traffic participant to generate an external environmental map identifying one or more second traffic features located in an exterior environment of the remote traffic participant, and by performing a diagnostic sensor cross check on on-board sensors by comparing the local environmental map with at least the external environmental map to detect any discrepancy between the one or more first traffic features and the one or more second traffic features which indicates that one or more of the on-board sensors is defective.

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An attenuator arrangement comprising at least a first attenuation path configured to couple between a signal processing chain, SPC, and a measurement apparatus; said SPC comprising a first and second SPC terminal, said SPC configured to apply one or both of a gain and phase change on a signal passed between the SPC terminals; said measurement apparatus configured to measure one or both of the gain and the phase change applied by SPC by coupling to and receiving signals from said SPC terminals; wherein one of said first SPC terminal and said second SPC terminal is coupled to the measurement apparatus through said first attenuation path; and wherein the at least first attenuation path of the attenuator arrangement is configured to provide, selectively, for attenuation of the signal to the measurement apparatus to make the signal power of the signals from said SPC terminals more equal.

An electronic device including a substrate having a first surface, a second surface, and one or more sidewalls. The electronic device may include a base metallization coupled to the first surface, one or more circuit layers formed on the second surface, and a dielectric layer on the one or more sidewalls and on the one or more circuit layers. The electronic device may include a metal layer formed on the dielectric layer. In some embodiments, one or more of the metal layer or the dielectric layer may form an ionic-contamination barrier. In some implementations, the metal layer, the dielectric layer, and one or more of the substrate or the base metallization layer may form a capacitor that extends around the one or more sides.

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Disclosed is a card clock recovery system (480; 500) for use in an NFC card transceiver (150; 450), wherein the NFC card transceiver (150; 450) is couplable to an NFC reader (110; 410). The card clock recovery system (480; 500) has: a phase lock loop (505) having: a phase/frequency detector (510), which is configured to receive a reference signal (512) provided at an RX port (476) of a matching network (475) during a receiving mode of the NFC transceiver (150; 450) or to receive a reference signal provided at the RX port (476) of the matching network (475) during a transmission mode of the NFC transceiver (150; 450), to receive a loop feedback signal (538), and to provide a phase error signal (518) that represents a phase difference between the reference signal (512) and the loop feedback signal (538); a loop filter (520) configured to receive a corrected phase error signal (756) that is derived from the phase error signal (518), and to provide a filtered corrected phase error signal (526); a controllable oscillator (530), which is configured to receive the filtered corrected phase error signal and to provide a controlled frequency output signal (534), which is provided as the card clock generation control signal (539) to a card clock generation unit (485) of an NFC card transceiver (150; 450), and as the loop feedback signal (538), via the loop feedback line (536), to the phase/frequency detector (510). The card clock recovery system (480; 500) further has a phase offset correction unit (700), which is configured to receive the phase error signal (518) provided by the phase/frequency detector and to provide the corrected phase error signal (756) to the loop filter (520), and which has a phase error sampling unit (720), a phase offset computation unit (730), and a phase subtractor unit (740).

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